module_roundkey4.v

来自「AES算法的verilog代码」· Verilog 代码 · 共 18 行

module roundkey4(rin4,kin4,rout_4,kout_4,clk); // ???????
input    [127:0]    rin4;
input    [127:0]    kin4;
input               clk;
output   [127:0]    rout_4;
output   [127:0]    kout_4;
wire     [127:0]    rout4;
wire     [127:0]    kout4;
reg      [127:0]    rout_4;
reg      [127:0]    kout_4;
round     rd4(.rin(rin4), .rout(rout4), .clk(clk));
keyexp4   kp4(.kin(kin4), .kout(kout4), .clk(clk));
always @ (posedge clk)
    begin
    rout_4<=rout4^kout4;
	 kout_4<=kout4;
	 end
endmodule