module_roundkey8.v

来自「AES算法的verilog代码」· Verilog 代码 · 共 18 行

module roundkey8(rin8,kin8,rout_8,kout_8,clk); // ???????
input    [127:0]    rin8;
input    [127:0]    kin8;
input               clk;
output   [127:0]    rout_8;
output   [127:0]    kout_8;
wire     [127:0]    rout8;
wire     [127:0]    kout8;
reg      [127:0]    rout_8;
reg      [127:0]    kout_8;
round     rd8(.rin(rin8), .rout(rout8), .clk(clk));
keyexp8   kp8(.kin(kin8), .kout(kout8), .clk(clk));
always @ (posedge clk)
    begin
    rout_8<=rout8^kout8;
	 kout_8<=kout8;
	 end
endmodule