module_roundkey9.v

来自「AES算法的verilog代码」· Verilog 代码 · 共 18 行

module roundkey9(rin9,kin9,rout_9,kout_9,clk); // ???????
input    [127:0]    rin9;
input    [127:0]    kin9;
input               clk;
output   [127:0]    rout_9;
output   [127:0]    kout_9;
wire     [127:0]    rout9;
wire     [127:0]    kout9;
reg      [127:0]    rout_9;
reg      [127:0]    kout_9;
round     rd9(.rin(rin9), .rout(rout9), .clk(clk));
keyexp9   kp9(.kin(kin9), .kout(kout9), .clk(clk));
always @ (posedge clk)
    begin
    rout_9<=rout9^kout9;
	 kout_9<=kout9;
	 end
endmodule