module_roundkey5.v

来自「AES算法的verilog代码」· Verilog 代码 · 共 18 行

module roundkey5(rin5,kin5,rout_5,kout_5,clk); // ???????
input    [127:0]    rin5;
input    [127:0]    kin5;
input               clk;
output   [127:0]    rout_5;
output   [127:0]    kout_5;
wire     [127:0]    rout5;
wire     [127:0]    kout5;
reg      [127:0]    rout_5;
reg      [127:0]    kout_5;
round     rd5(.rin(rin5), .rout(rout5), .clk(clk));
keyexp5   kp5(.kin(kin5), .kout(kout5), .clk(clk));
always @ (posedge clk)
    begin
    rout_5<=rout5^kout5;
	 kout_5<=kout5;
	 end
endmodule