module_roundkey7.v

来自「AES算法的verilog代码」· Verilog 代码 · 共 18 行

module roundkey7(rin7,kin7,rout_7,kout_7,clk); // ???????
input    [127:0]    rin7;
input    [127:0]    kin7;
input               clk;
output   [127:0]    rout_7;
output   [127:0]    kout_7;
wire     [127:0]    rout7;
wire     [127:0]    kout7;
reg      [127:0]    rout_7;
reg      [127:0]    kout_7;
round     rd7(.rin(rin7), .rout(rout7), .clk(clk));
keyexp7   kp7(.kin(kin7), .kout(kout7), .clk(clk));
always @ (posedge clk)
    begin
    rout_7<=rout7^kout7;
	 kout_7<=kout7;
	 end
endmodule