module_roundkey1.v

来自「AES算法的verilog代码」· Verilog 代码 · 共 21 行

module roundkey1(rin1,kin1,rout_1,kout_1,clk); // ???????
input    [127:0]    rin1;
input    [127:0]    kin1;
input               clk;
output   [127:0]    rout_1;
output   [127:0]    kout_1;
wire     [127:0]    rout1;
wire     [127:0]    kout1;
reg      [127:0]    rout_1;
reg      [127:0]    kout_1;
round     rd1(.rin(rin1), .rout(rout1), .clk(clk));
keyexp1   kp1(.kin(kin1), .kout(kout1), .clk(clk));
always @ (posedge clk)
   begin
    rout_1<=rout1^kout1;
	 kout_1<=kout1;
   end
endmodule