module_roundkey2.v

来自「AES算法的verilog代码」· Verilog 代码 · 共 18 行

module roundkey2(rin2,kin2,rout_2,kout_2,clk); // ???????
input    [127:0]    rin2;
input    [127:0]    kin2;
input               clk;
output   [127:0]    rout_2;
output   [127:0]    kout_2;
wire     [127:0]    rout2;
wire     [127:0]    kout2;
reg      [127:0]    rout_2;
reg      [127:0]    kout_2;
round     rd2(.rin(rin2), .rout(rout2), .clk(clk));
keyexp2   kp2(.kin(kin2), .kout(kout2), .clk(clk));
always @ (posedge clk)
    begin
    rout_2<=rout2^kout2;
	 kout_2<=kout2;
	 end
endmodule