module_keyexp9.v

来自「AES算法的verilog代码」· Verilog 代码 · 共 43 行

module keyexp9(kin,kout,clk); // ???????
input  [127:0]    kin;
input             clk;
output [127:0]    kout;
reg    [127:0]    kout;
reg    [31:0]     w0;
reg    [31:0]     w1;
reg    [31:0]     w2;
reg    [31:0]     w3;
reg    [31:0]     kw0;
reg    [31:0]     kw1;
reg    [31:0]     kw2;
reg    [31:0]     kw3;
reg    [31:0]     w_3;
wire   [31:0]     wo_3;
always  @ (posedge clk)
    begin
	  w0<=kin[127:96];
	  w1<=kin[95:64];
	  w2<=kin[63:32];
	  w3<=kin[31:0];
	 end
always  @ (posedge clk)
    begin
	  w_3[31:8]<=w3[23:0];
	  w_3[7:0]<=w3[31:24];
	 end
  box10  k0(.din10(w_3[31:24]), .dout10(wo_3[31:24]), .clk(clk));
  box10  k1(.din10(w_3[23:16]), .dout10(wo_3[23:16]), .clk(clk));
  box10  k2(.din10(w_3[15:8]), .dout10(wo_3[15:8]), .clk(clk));
  box10  k3(.din10(w_3[7:0]), .dout10(wo_3[7:0]), .clk(clk));
always @ (posedge clk)
     begin
	   kw0<=w0^wo_3^32'h1b000000;
	   kw1<=kw0^w1;
	   kw2<=kw1^w2;
	   kw3<=kw2^w3;
      kout[127:96]<=kw0;
	   kout[95:64]<=kw1;
	   kout[63:32]<=kw2;
	   kout[31:0]<=kw3;
	  end
endmodule