📄 fredevider.vhd
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LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY FreDevider IS
PORT
(Clkin:IN Std_Logic;
Clkout:OUT Std_Logic);
END;
ARCHITECTURE Devider OF FreDevider IS
CONSTANT N:Integer:=499;
signal counter:Integer range 0 to N;
signal Clk:Std_Logic;
BEGIN
PROCESS(Clkin)
begin
IF rising_edge(Clkin)THEN
IF Counter=N then
counter<=0;
Clk<=not clk;
else
counter<=counter+1;
end if;
end if;
end process;
clkout<=clk;
end;
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