📄 fredevider.rpt
字号:
- 6 - B 12 DFFE + 0 1 1 0 Clk (:12)
- 2 - B 11 OR2 s 0 3 0 1 ~50~1
- 1 - B 09 OR2 s 0 4 0 1 ~50~2
- 5 - B 09 OR2 ! 0 4 0 9 :50
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\kkk\fredevider.rpt
fredevider
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 6/ 96( 6%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\kkk\fredevider.rpt
fredevider
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 10 Clkin
Device-Specific Information: f:\kkk\fredevider.rpt
fredevider
** EQUATIONS **
Clkin : INPUT;
-- Node name is ':12' = 'Clk'
-- Equation name is 'Clk', location is LC6_B12, type is buried.
Clk = DFFE( _EQ001, GLOBAL( Clkin), VCC, VCC, VCC);
_EQ001 = Clk & !_LC5_B9
# !Clk & _LC5_B9;
-- Node name is 'Clkout'
-- Equation name is 'Clkout', type is output
Clkout = Clk;
-- Node name is ':11' = 'counter0'
-- Equation name is 'counter0', location is LC7_B9, type is buried.
counter0 = DFFE(!counter0, GLOBAL( Clkin), VCC, VCC, VCC);
-- Node name is ':10' = 'counter1'
-- Equation name is 'counter1', location is LC6_B9, type is buried.
counter1 = DFFE( _EQ002, GLOBAL( Clkin), VCC, VCC, VCC);
_EQ002 = !counter0 & counter1 & !_LC5_B9
# counter0 & !counter1 & !_LC5_B9;
-- Node name is ':9' = 'counter2'
-- Equation name is 'counter2', location is LC4_B9, type is buried.
counter2 = DFFE( _EQ003, GLOBAL( Clkin), VCC, VCC, VCC);
_EQ003 = !counter1 & counter2 & !_LC5_B9
# !counter0 & counter2 & !_LC5_B9
# counter0 & counter1 & !counter2 & !_LC5_B9;
-- Node name is ':8' = 'counter3'
-- Equation name is 'counter3', location is LC3_B9, type is buried.
counter3 = DFFE( _EQ004, GLOBAL( Clkin), VCC, VCC, VCC);
_EQ004 = counter3 & !_LC2_B9 & !_LC5_B9
# !counter3 & _LC2_B9 & !_LC5_B9;
-- Node name is ':7' = 'counter4'
-- Equation name is 'counter4', location is LC8_B11, type is buried.
counter4 = DFFE( _EQ005, GLOBAL( Clkin), VCC, VCC, VCC);
_EQ005 = counter4 & !_LC5_B9 & !_LC8_B9
# !counter4 & !_LC5_B9 & _LC8_B9;
-- Node name is ':6' = 'counter5'
-- Equation name is 'counter5', location is LC3_B11, type is buried.
counter5 = DFFE( _EQ006, GLOBAL( Clkin), VCC, VCC, VCC);
_EQ006 = !counter4 & counter5 & !_LC5_B9
# counter5 & !_LC5_B9 & !_LC8_B9
# counter4 & !counter5 & !_LC5_B9 & _LC8_B9;
-- Node name is ':5' = 'counter6'
-- Equation name is 'counter6', location is LC4_B11, type is buried.
counter6 = DFFE( _EQ007, GLOBAL( Clkin), VCC, VCC, VCC);
_EQ007 = counter6 & !_LC1_B11 & !_LC5_B9
# !counter6 & _LC1_B11 & !_LC5_B9;
-- Node name is ':4' = 'counter7'
-- Equation name is 'counter7', location is LC5_B11, type is buried.
counter7 = DFFE( _EQ008, GLOBAL( Clkin), VCC, VCC, VCC);
_EQ008 = !counter6 & counter7 & !_LC5_B9
# counter7 & !_LC1_B11 & !_LC5_B9
# counter6 & !counter7 & _LC1_B11 & !_LC5_B9;
-- Node name is ':3' = 'counter8'
-- Equation name is 'counter8', location is LC7_B11, type is buried.
counter8 = DFFE( _EQ009, GLOBAL( Clkin), VCC, VCC, VCC);
_EQ009 = !counter7 & counter8 & !_LC5_B9
# counter8 & !_LC5_B9 & !_LC6_B11
# counter7 & !counter8 & !_LC5_B9 & _LC6_B11;
-- Node name is '|LPM_ADD_SUB:121|addcore:adder|:83' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B9', type is buried
_LC2_B9 = LCELL( _EQ010);
_EQ010 = counter0 & counter1 & counter2;
-- Node name is '|LPM_ADD_SUB:121|addcore:adder|:87' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B9', type is buried
_LC8_B9 = LCELL( _EQ011);
_EQ011 = counter0 & counter1 & counter2 & counter3;
-- Node name is '|LPM_ADD_SUB:121|addcore:adder|:95' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B11', type is buried
_LC1_B11 = LCELL( _EQ012);
_EQ012 = counter4 & counter5 & _LC8_B9;
-- Node name is '|LPM_ADD_SUB:121|addcore:adder|:99' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B11', type is buried
_LC6_B11 = LCELL( _EQ013);
_EQ013 = counter6 & _LC1_B11;
-- Node name is '~50~1'
-- Equation name is '~50~1', location is LC2_B11, type is buried.
-- synthesized logic cell
_LC2_B11 = LCELL( _EQ014);
_EQ014 = !counter6
# !counter7
# !counter8;
-- Node name is '~50~2'
-- Equation name is '~50~2', location is LC1_B9, type is buried.
-- synthesized logic cell
_LC1_B9 = LCELL( _EQ015);
_EQ015 = !counter5
# _LC2_B11
# counter3
# !counter4;
-- Node name is ':50'
-- Equation name is '_LC5_B9', type is buried
!_LC5_B9 = _LC5_B9~NOT;
_LC5_B9~NOT = LCELL( _EQ016);
_EQ016 = counter2
# !counter1
# !counter0
# _LC1_B9;
Project Information f:\kkk\fredevider.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 21,738K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -