compile.cfg

RTL in Verilog (Vending Machine)

[View]
Entity=vending_machine
Architecture=
TopLevelType=3
[file:.\src\vending_machine.v]
File Time Lo=2046703264
File Time Hi=29998141
Enabled=1
State=Modified
[file:.\src\integer2bcd.v]
File Time Lo=1346096406
File Time Hi=29998089
Enabled=1
State=Compiled
[file:.\src\waveform.awf]
File Time Lo=-409670282
File Time Hi=29998141
Enabled=1
State=Modified