integer2bcd.v

RTL in Verilog (Vending Machine)

//-----------------------------------------------------------------------------
//
// Title       : integer2bcd
// Design      : vending_machine
// Author      : 茄己痹
// Company     : POSTECH
//
//-----------------------------------------------------------------------------
//
// File        : integer2bcd.v
// Generated   : Mon Apr 13 15:55:23 2009
// From        : interface description file
// By          : Itf2Vhdl ver. 1.21
//
//-----------------------------------------------------------------------------
//
// Description : 
//
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ns

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {integer2bcd}}
module integer2bcd ( number, out_bcd_0 ,out_bcd_1 ,out_bcd_2 ,out_bcd_3 ,out_bcd_4 );

output [3:0] out_bcd_1 ;
reg [3:0] out_bcd_1 ;
output [3:0] out_bcd_2 ;
reg [3:0] out_bcd_2 ;
output [3:0] out_bcd_3 ;
reg [3:0] out_bcd_3 ;
output [3:0] out_bcd_4 ;
reg [3:0] out_bcd_4 ;
output [3:0] out_bcd_0 ;
reg [3:0] out_bcd_0 ;

input [31:0] number ;
wire [31:0] number;

//}} End of automatically maintained section

// -- Enter your statements here -- //	
always @ (number)
begin	
	case ((number % 32'd100000) / 32'd10000)
		32'd0: out_bcd_0 <= 4'b0000;
		32'd1: out_bcd_0 <= 4'b0001;
		32'd2: out_bcd_0 <= 4'b0010;
		32'd3: out_bcd_0 <= 4'b0011;
		32'd4: out_bcd_0 <= 4'b0100;
		32'd5: out_bcd_0 <= 4'b1000;
		32'd6: out_bcd_0 <= 4'b1001;
		32'd7: out_bcd_0 <= 4'b1010;
		32'd8: out_bcd_0 <= 4'b1011;
		32'd9: out_bcd_0 <= 4'b1100;
	endcase
	case ((number % 32'd10000) / 32'd1000)
		32'd0: out_bcd_1 <= 4'b0000;
		32'd1: out_bcd_1 <= 4'b0001;
		32'd2: out_bcd_1 <= 4'b0010;
		32'd3: out_bcd_1 <= 4'b0011;
		32'd4: out_bcd_1 <= 4'b0100;
		32'd5: out_bcd_1 <= 4'b1000;
		32'd6: out_bcd_1 <= 4'b1001;
		32'd7: out_bcd_1 <= 4'b1010;
		32'd8: out_bcd_1 <= 4'b1011;
		32'd9: out_bcd_1 <= 4'b1100;
	endcase		
	case ((number % 32'd1000) / 32'd100)
		32'd0: out_bcd_2 <= 4'b0000;
		32'd1: out_bcd_2 <= 4'b0001;
		32'd2: out_bcd_2 <= 4'b0010;
		32'd3: out_bcd_2 <= 4'b0011;
		32'd4: out_bcd_2 <= 4'b0100;
		32'd5: out_bcd_2 <= 4'b1000;
		32'd6: out_bcd_2 <= 4'b1001;
		32'd7: out_bcd_2 <= 4'b1010;
		32'd8: out_bcd_2 <= 4'b1011;
		32'd9: out_bcd_2 <= 4'b1100;
	endcase	
	case ((number % 32'd100) / 32'd10)
		32'd0: out_bcd_3 <= 4'b0000;
		32'd1: out_bcd_3 <= 4'b0001;
		32'd2: out_bcd_3 <= 4'b0010;
		32'd3: out_bcd_3 <= 4'b0011;
		32'd4: out_bcd_3 <= 4'b0100;
		32'd5: out_bcd_3 <= 4'b1000;
		32'd6: out_bcd_3 <= 4'b1001;
		32'd7: out_bcd_3 <= 4'b1010;
		32'd8: out_bcd_3 <= 4'b1011;
		32'd9: out_bcd_3 <= 4'b1100;
	endcase	
	case (number % 32'd10) 
		32'd0: out_bcd_4 <= 4'b0000;
		32'd1: out_bcd_4 <= 4'b0001;
		32'd2: out_bcd_4 <= 4'b0010;
		32'd3: out_bcd_4 <= 4'b0011;
		32'd4: out_bcd_4 <= 4'b0100;
		32'd5: out_bcd_4 <= 4'b1000;
		32'd6: out_bcd_4 <= 4'b1001;
		32'd7: out_bcd_4 <= 4'b1010;
		32'd8: out_bcd_4 <= 4'b1011;
		32'd9: out_bcd_4 <= 4'b1100;
	endcase
end	
endmodule