1vending_machine.mgf

RTL in Verilog (Vending Machine)

)
I 000052 55 2758          1239607219410 integer2bcd
(_unit VERILOG 6.1285.6.606 (integer2bcd 0 25 (integer2bcd 0 25 ))
	(_version v147)
	(_time 1239607219140 2009.04.13 16:20:19)
	(_source (\./src/integer2bcd.v\ VERILOG (\./src/integer2bcd.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_code 32613937656462243237256866)
	(_entity
		(_time 1239607219140)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs      )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[31:0]wire~ 0 25 (_array ~wire ((_downto (i 31) (i 0))))))
		(_port (_internal number ~[31:0]wire~ 0 25 (_architecture (_in ))) (_net  (_scalared) ) (_flags1))
		(_type (_internal ~[3:0]reg~ 0 25 (_array ~reg ((_downto (i 3) (i 0))))))
		(_port (_internal out_bcd_1 ~[3:0]reg~ 0 25 (_architecture (_out ))) (_reg ) (_simple) (_flags1))
		(_port (_internal out_bcd_2 ~[3:0]reg~ 0 25 (_architecture (_out ))) (_reg ) (_simple) (_flags1))
		(_port (_internal out_bcd_3 ~[3:0]reg~ 0 25 (_architecture (_out ))) (_reg ) (_simple) (_flags1))
		(_port (_internal out_bcd_4 ~[3:0]reg~ 0 25 (_architecture (_out ))) (_reg ) (_simple) (_flags1))
		(_port (_internal out_bcd_0 ~[3:0]reg~ 0 25 (_architecture (_out ))) (_reg ) (_simple) (_flags1))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~vbit (vl verilog_logic vbit)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~logic (vl verilog_logic logic)))			
		(_type (_external ~logic_reg (vl verilog_logic logic)))			
		(_type (_external ~logic_bit (vl verilog_logic vbit)))
		(_type (_external ~shortreal (vl verilog_logic real)))				
		(_type (_external ~string (vl verilog_logic string)))	
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(@ALWAYS#44_0@ (_architecture 0 0 44 (_process 
				(_target(5)(1)(2)(3)(4))
				(_read)
				(_sensitivity(0))
				(_need_init)
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . integer2bcd 2 -1)

)
I 000046 55 1822          1239607843562 $root
(_unit VERILOG 6.1285.6.606 ($root 0 0 ($root 0 0 ))
	(_version v147)
	(_time 1239607843250 2009.04.13 16:30:43)
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_code 10141c16124712064617044e45)
	(_entity
		(_time 1239607843250)
		(_use )
	)
	(_parameters top_design   dbg   accs      )
	(_attribute top_design )
	(_object
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~vbit (vl verilog_logic vbit)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~logic (vl verilog_logic logic)))			
		(_type (_external ~logic_reg (vl verilog_logic logic)))			
		(_type (_external ~logic_bit (vl verilog_logic vbit)))
		(_type (_external ~shortreal (vl verilog_logic real)))				
		(_type (_external ~string (vl verilog_logic string)))	
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation vending_machine 0 0 (_entity .  vending_machine)
	)
	(_model . $root 1 -1)

)
I 000056 55 5567          1239607843566 vending_machine
(_unit VERILOG 6.1285.6.606 (vending_machine 0 25 (vending_machine 0 25 ))
	(_version v147)
	(_time 1239607843250 2009.04.13 16:30:43)
	(_source (\./src/vending_machine.v\ VERILOG (\./src/vending_machine.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_code 10111e17154711064544094a14)
	(_entity
		(_time 1239607843250)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs      )
	(_attribute nb_assign )
	(_object
		(_port (_internal return_thousand ~wire 0 25 (_architecture (_out ))) (_net  (_scalared) ) (_simple) (_flags1))
		(_port (_internal return_f_hundred ~wire 0 25 (_architecture (_out ))) (_net  (_scalared) ) (_simple) (_flags1))
		(_port (_internal return_hundred ~wire 0 25 (_architecture (_out ))) (_net  (_scalared) ) (_simple) (_flags1))
		(_type (_internal ~[3:0]reg~ 0 25 (_array ~reg ((_downto (i 3) (i 0))))))
		(_port (_internal current_total_4 ~[3:0]reg~ 0 25 (_architecture (_out ))) (_reg ) (_flags1))
		(_port (_internal current_total_3 ~[3:0]reg~ 0 25 (_architecture (_out ))) (_reg ) (_flags1))
		(_port (_internal current_total_2 ~[3:0]reg~ 0 25 (_architecture (_out ))) (_reg ) (_flags1))
		(_port (_internal current_total_1 ~[3:0]reg~ 0 25 (_architecture (_out ))) (_reg ) (_flags1))
		(_port (_internal current_total_0 ~[3:0]reg~ 0 25 (_architecture (_out ))) (_reg ) (_flags1))
		(_port (_internal sufficient_item_4 ~reg 0 25 (_architecture (_out ))) (_reg ) (_simple) (_flags1))
		(_port (_internal sufficient_item_3 ~reg 0 25 (_architecture (_out ))) (_reg ) (_simple) (_flags1))
		(_port (_internal sufficient_item_2 ~reg 0 25 (_architecture (_out ))) (_reg ) (_simple) (_flags1))
		(_port (_internal sufficient_item_1 ~reg 0 25 (_architecture (_out ))) (_reg ) (_simple) (_flags1))
		(_port (_internal output_item ~reg 0 25 (_architecture (_out ))) (_reg ) (_simple) (_flags1))
		(_port (_internal clk ~wire 0 25 (_architecture (_in ))) (_net  (_scalared) ) (_nonbaction) (_noforceassign))
		(_port (_internal return_trigger ~wire 0 25 (_architecture (_in ))) (_net  (_scalared) ) (_flags1))
		(_port (_internal sel_item_4 ~wire 0 25 (_architecture (_in ))) (_net  (_scalared) ) (_flags1))
		(_port (_internal sel_item_3 ~wire 0 25 (_architecture (_in ))) (_net  (_scalared) ) (_flags1))
		(_port (_internal sel_item_2 ~wire 0 25 (_architecture (_in ))) (_net  (_scalared) ) (_flags1))
		(_port (_internal sel_item_1 ~wire 0 25 (_architecture (_in ))) (_net  (_scalared) ) (_flags1))
		(_port (_internal input_thousand ~wire 0 25 (_architecture (_in ))) (_net  (_scalared) ) (_flags1))
		(_port (_internal input_f_hundred ~wire 0 25 (_architecture (_in ))) (_net  (_scalared) ) (_flags1))
		(_port (_internal input_hundred ~wire 0 25 (_architecture (_in ))) (_net  (_scalared) ) (_flags1))
		(_port (_internal neg_reset ~wire 0 25 (_architecture (_in ))) (_net  (_scalared) ) (_nonbaction) (_noforceassign))
		(_type (_internal ~[2:0]reg~ 0 88 (_array ~reg ((_downto (i 2) (i 0))))))
		(_signal (_internal state ~[2:0]reg~ 0 88 (_architecture (_uni ))) (_reg ) (_flags1))
		(_signal (_internal next_state ~[2:0]reg~ 0 89 (_architecture (_uni ))) (_reg ) (_simple) (_flags1))
		(_type (_internal ~[31:0]reg~ 0 90 (_array ~reg ((_downto (i 31) (i 0))))))
		(_signal (_internal qt_coin ~[31:0]reg~ 0 90 (_architecture (_uni ))) (_reg ) (_flags1))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~vbit (vl verilog_logic vbit)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~logic (vl verilog_logic logic)))			
		(_type (_external ~logic_reg (vl verilog_logic logic)))			
		(_type (_external ~logic_bit (vl verilog_logic vbit)))
		(_type (_external ~shortreal (vl verilog_logic real)))				
		(_type (_external ~string (vl verilog_logic string)))	
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(@ALWAYS#106_0@ (_architecture 0 0 106 (_process 
				(_target(24)(25)(11)(10)(9)(8)(12))
				(_read(25)(11)(10)(9)(8))
				(_sensitivity(14)(15)(16)(17)(18)(19)(20)(21)(23))
				(_need_init)
			)))
			(@ALWAYS#185_1@ (_architecture 1 0 185 (_process 
				(_target(25)(23))
				(_read(13)(22)(24))
				(_need_init)
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit define_next_state begin 0 107
		(_scope
			(_unit Idle begin 0 110
			)
			(_unit Count_Coins begin 0 115
			)
			(_unit Give_Change begin 0 128
			)
			(_unit Select_Items begin 0 132
			)
			(_unit Dispense begin 0 177
			)
		)
		)
		(_unit curr begin 0 186
		)
	)
	(_instantiation integer2bcd 0 102 (_entity .  integer2bcd)
		(_port
			((qt_coin))
			((current_total_0))
			((current_total_1))
			((current_total_2))
			((current_total_3))
			((current_total_4))
		)
	)
	(_model . vending_machine 3 -1)

)
I 000046 55 1822          1239607884157 $root
(_unit VERILOG 6.1285.6.606 ($root 0 0 ($root 0 0 ))
	(_version v147)
	(_time 1239607883937 2009.04.13 16:31:23)
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_code fffdfdaeaba8fde9a9f8eba1aa)
	(_entity
		(_time 1239607883937)
		(_use )
	)
	(_parameters top_design   dbg   accs      )
	(_attribute top_design )
	(_object
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~vbit (vl verilog_logic vbit)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~logic (vl verilog_logic logic)))			
		(_type (_external ~logic_reg (vl verilog_logic logic)))			
		(_type (_external ~logic_bit (vl verilog_logic vbit)))
		(_type (_external ~shortreal (vl verilog_logic real)))				
		(_type (_external ~string (vl verilog_logic string)))	
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation vending_machine 0 0 (_entity .  vending_machine)
	)
	(_model . $root 1 -1)

)
I 000056 55 5639          1239607884161 vending_machine
(_unit VERILOG 6.1285.6.606 (vending_machine 0 25 (vending_machine 0 25 ))
	(_version v147)
	(_time 1239607883937 2009.04.13 16:31:23)
	(_source (\./src/vending_machine.v\ VERILOG (\./src/vending_machine.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_code fff8ffafaca8fee9aaabe6a5fb)
	(_entity
		(_time 1239607883937)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs      )
	(_attribute nb_assign )
	(_object
		(_port (_internal return_thousand ~wire 0 25 (_architecture (_out ))) (_net  (_scalared) ) (_simple) (_flags1))
		(_port (_internal return_f_hundred ~wire 0 25 (_architecture (_out ))) (_net  (_scalared) ) (_simple) (_flags1))
		(_port (_internal return_hundred ~wire 0 25 (_architecture (_out ))) (_net  (_scalared) ) (_simple) (_flags1))
		(_type (_internal ~[3:0]wire~ 0 25 (_array ~wire ((_downto (i 3) (i 0))))))
		(_port (_intern