1vending_machine.mgf

RTL in Verilog (Vending Machine)

		(_type (_external ~logic_reg (vl verilog_logic logic)))			
		(_type (_external ~logic_bit (vl verilog_logic vbit)))
		(_type (_external ~shortreal (vl verilog_logic real)))				
		(_type (_external ~string (vl verilog_logic string)))	
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(@ALWAYS#44_0@ (_architecture 0 0 44 (_process 
				(_target(5)(1)(2)(3)(4))
				(_read)
				(_sensitivity(0))
				(_need_init)
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . integer2bcd 2 -1)

)
I 000046 55 1883          1239607087531 $root
(_unit VERILOG 6.1285.6.606 ($root 0 0 ($root 0 0 ))
	(_version v147)
	(_time 1239607087265 2009.04.13 16:18:07)
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_code ffa9aeaeaba8fde9a9f8eba1aa)
	(_entity
		(_time 1239607087265)
		(_use )
	)
	(_parameters top_design   dbg   accs      )
	(_attribute top_design )
	(_object
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~vbit (vl verilog_logic vbit)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~logic (vl verilog_logic logic)))			
		(_type (_external ~logic_reg (vl verilog_logic logic)))			
		(_type (_external ~logic_bit (vl verilog_logic vbit)))
		(_type (_external ~shortreal (vl verilog_logic real)))				
		(_type (_external ~string (vl verilog_logic string)))	
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation vending_machine 0 0 (_entity .  vending_machine)
	)
	(_instantiation integer2bcd 0 0 (_entity .  integer2bcd)
	)
	(_model . $root 1 -1)

)
I 000052 55 2758          1239607087535 integer2bcd
(_unit VERILOG 6.1285.6.606 (integer2bcd 0 25 (integer2bcd 0 25 ))
	(_version v147)
	(_time 1239607087265 2009.04.13 16:18:07)
	(_source (\./src/integer2bcd.v\ VERILOG (\./src/integer2bcd.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_code ffada3affca9afe9fffae8a5ab)
	(_entity
		(_time 1239607087265)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs      )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[31:0]wire~ 0 25 (_array ~wire ((_downto (i 31) (i 0))))))
		(_port (_internal number ~[31:0]wire~ 0 25 (_architecture (_in ))) (_net  (_scalared) ) (_flags1))
		(_type (_internal ~[3:0]reg~ 0 25 (_array ~reg ((_downto (i 3) (i 0))))))
		(_port (_internal out_bcd_1 ~[3:0]reg~ 0 25 (_architecture (_out ))) (_reg ) (_simple) (_flags1))
		(_port (_internal out_bcd_2 ~[3:0]reg~ 0 25 (_architecture (_out ))) (_reg ) (_simple) (_flags1))
		(_port (_internal out_bcd_3 ~[3:0]reg~ 0 25 (_architecture (_out ))) (_reg ) (_simple) (_flags1))
		(_port (_internal out_bcd_4 ~[3:0]reg~ 0 25 (_architecture (_out ))) (_reg ) (_simple) (_flags1))
		(_port (_internal out_bcd_0 ~[3:0]reg~ 0 25 (_architecture (_out ))) (_reg ) (_simple) (_flags1))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~vbit (vl verilog_logic vbit)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~logic (vl verilog_logic logic)))			
		(_type (_external ~logic_reg (vl verilog_logic logic)))			
		(_type (_external ~logic_bit (vl verilog_logic vbit)))
		(_type (_external ~shortreal (vl verilog_logic real)))				
		(_type (_external ~string (vl verilog_logic string)))	
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(@ALWAYS#44_0@ (_architecture 0 0 44 (_process 
				(_target(5)(1)(2)(3)(4))
				(_read)
				(_sensitivity(0))
				(_need_init)
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . integer2bcd 2 -1)

)
I 000046 55 1883          1239607191266 $root
(_unit VERILOG 6.1285.6.606 ($root 0 0 ($root 0 0 ))
	(_version v147)
	(_time 1239607190968 2009.04.13 16:19:50)
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_code 16131610124114004011024843)
	(_entity
		(_time 1239607190968)
		(_use )
	)
	(_parameters top_design   dbg   accs      )
	(_attribute top_design )
	(_object
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~vbit (vl verilog_logic vbit)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~logic (vl verilog_logic logic)))			
		(_type (_external ~logic_reg (vl verilog_logic logic)))			
		(_type (_external ~logic_bit (vl verilog_logic vbit)))
		(_type (_external ~shortreal (vl verilog_logic real)))				
		(_type (_external ~string (vl verilog_logic string)))	
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation vending_machine 0 0 (_entity .  vending_machine)
	)
	(_instantiation integer2bcd 0 0 (_entity .  integer2bcd)
	)
	(_model . $root 1 -1)

)
I 000052 55 2758          1239607191270 integer2bcd
(_unit VERILOG 6.1285.6.606 (integer2bcd 0 25 (integer2bcd 0 25 ))
	(_version v147)
	(_time 1239607190968 2009.04.13 16:19:50)
	(_source (\./src/integer2bcd.v\ VERILOG (\./src/integer2bcd.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_code 16171b11454046001614014c42)
	(_entity
		(_time 1239607190968)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs      )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[31:0]wire~ 0 25 (_array ~wire ((_downto (i 31) (i 0))))))
		(_port (_internal number ~[31:0]wire~ 0 25 (_architecture (_in ))) (_net  (_scalared) ) (_flags1))
		(_type (_internal ~[3:0]reg~ 0 25 (_array ~reg ((_downto (i 3) (i 0))))))
		(_port (_internal out_bcd_1 ~[3:0]reg~ 0 25 (_architecture (_out ))) (_reg ) (_simple) (_flags1))
		(_port (_internal out_bcd_2 ~[3:0]reg~ 0 25 (_architecture (_out ))) (_reg ) (_simple) (_flags1))
		(_port (_internal out_bcd_3 ~[3:0]reg~ 0 25 (_architecture (_out ))) (_reg ) (_simple) (_flags1))
		(_port (_internal out_bcd_4 ~[3:0]reg~ 0 25 (_architecture (_out ))) (_reg ) (_simple) (_flags1))
		(_port (_internal out_bcd_0 ~[3:0]reg~ 0 25 (_architecture (_out ))) (_reg ) (_simple) (_flags1))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~vbit (vl verilog_logic vbit)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~logic (vl verilog_logic logic)))			
		(_type (_external ~logic_reg (vl verilog_logic logic)))			
		(_type (_external ~logic_bit (vl verilog_logic vbit)))
		(_type (_external ~shortreal (vl verilog_logic real)))				
		(_type (_external ~string (vl verilog_logic string)))	
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(@ALWAYS#45_0@ (_architecture 0 0 45 (_process 
				(_target(5)(1)(2)(3)(4))
				(_read)
				(_sensitivity(0))
				(_need_init)
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . integer2bcd 2 -1)

)
I 000046 55 1883          1239607219406 $root
(_unit VERILOG 6.1285.6.606 ($root 0 0 ($root 0 0 ))
	(_version v147)
	(_time 1239607219140 2009.04.13 16:20:19)
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_code 32653436326530246435266c67)
	(_entity
		(_time 1239607219140)
		(_use )
	)
	(_parameters top_design   dbg   accs      )
	(_attribute top_design )
	(_object
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~vbit (vl verilog_logic vbit)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~logic (vl verilog_logic logic)))			
		(_type (_external ~logic_reg (vl verilog_logic logic)))			
		(_type (_external ~logic_bit (vl verilog_logic vbit)))
		(_type (_external ~shortreal (vl verilog_logic real)))				
		(_type (_external ~string (vl verilog_logic string)))	
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation vending_machine 0 0 (_entity .  vending_machine)
	)
	(_instantiation integer2bcd 0 0 (_entity .  integer2bcd)
	)
	(_model . $root 1 -1)