modelsim_test_v.sdo

BJ-EPM240V2实验例程以及说明文档实验之十五Quartus II调用ModelSim仿真实例

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EPM240T100C5 Package TQFP100
// 

// 
// This SDF file should be used for ModelSim (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "modelsim_test")
  (DATE "05/23/2000 11:14:24")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 7.0 Build 33 02/05/2007 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "maxii_io")
    (INSTANCE clk\~I)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1132:1132:1132) (1132:1132:1132))
      )
    )
  )
  (CELL
    (CELLTYPE "maxii_io")
    (INSTANCE rst_n\~I)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1132:1132:1132) (1132:1132:1132))
      )
    )
  )
  (CELL
    (CELLTYPE "maxii_asynch_lcell")
    (INSTANCE div\~reg0_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (940:940:940) (894:894:894))
        (IOPATH datac regin (804:804:804) (804:804:804))
      )
    )
  )
  (CELL
    (CELLTYPE "maxii_lcell_register")
    (INSTANCE div\~reg0_I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (4406:4406:4406) (4706:4706:4706))
        (PORT clk (2079:2079:2079) (1814:1814:1814))
        (IOPATH (posedge clk) regout (376:376:376) (376:376:376))
        (IOPATH (posedge aclr) regout (577:577:577) (577:577:577))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (333:333:333))
      (HOLD datain (posedge clk) (221:221:221))
    )
  )
  (CELL
    (CELLTYPE "maxii_io")
    (INSTANCE div\~I)
    (DELAY
      (ABSOLUTE
        (PORT datain (758:758:758) (808:808:808))
        (IOPATH datain padio (2322:2322:2322) (2322:2322:2322))
      )
    )
  )
)