myosctest_v.sdo

BJ-EPM240V2实验例程以及说明文档实验之十三MAX II内部震荡时钟实例

// Copyright (C) 1991-2008 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EPM240T100C5 Package TQFP100
// 

// 
// This SDF file should be used for ModelSim (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "myosctest")
  (DATE "02/06/2009 14:18:29")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 8.1 Build 163 10/28/2008 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "maxii_ufm")
    (INSTANCE internal_osc\|internal_osc_altufm_osc_rv5_component\|maxii_ufm_block1)
    (DELAY
      (ABSOLUTE
        (PORT drdin (0:0:0) (0:0:0))
        (PORT drclk (0:0:0) (0:0:0))
        (PORT drshft (0:0:0) (0:0:0))
        (PORT ardin (0:0:0) (0:0:0))
        (PORT arclk (0:0:0) (0:0:0))
        (PORT arshft (0:0:0) (0:0:0))
        (PORT oscena (1015:1015:1015) (1015:1015:1015))
        (IOPATH (posedge oscena) osc (180000:180000:180000) (180000:180000:180000))
      )
    )
  )
  (CELL
    (CELLTYPE "maxii_io")
    (INSTANCE rst_n\~I)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1163:1163:1163) (1163:1163:1163))
      )
    )
  )
  (CELL
    (CELLTYPE "maxii_asynch_lcell")
    (INSTANCE cnt\[0\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (931:931:931) (931:931:931))
        (IOPATH datad regin (591:591:591) (591:591:591))
      )
    )
  )
  (CELL
    (CELLTYPE "maxii_lcell_register")
    (INSTANCE cnt\[0\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2639:2639:2639) (2639:2639:2639))
        (PORT clk (4378:4378:4378) (4378:4378:4378))
        (IOPATH (posedge clk) regout (376:376:376) (376:376:376))
        (IOPATH (posedge aclr) regout (577:577:577) (577:577:577))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (333:333:333))
      (HOLD datain (posedge clk) (221:221:221))
    )
  )
  (CELL
    (CELLTYPE "maxii_asynch_lcell")
    (INSTANCE cnt\[1\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (969:969:969) (969:969:969))
        (PORT datad (935:935:935) (935:935:935))
        (IOPATH datac regin (804:804:804) (804:804:804))
        (IOPATH datad regin (591:591:591) (591:591:591))
      )
    )
  )
  (CELL
    (CELLTYPE "maxii_lcell_register")
    (INSTANCE cnt\[1\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2639:2639:2639) (2639:2639:2639))
        (PORT clk (4378:4378:4378) (4378:4378:4378))
        (IOPATH (posedge clk) regout (376:376:376) (376:376:376))
        (IOPATH (posedge aclr) regout (577:577:577) (577:577:577))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (333:333:333))
      (HOLD datain (posedge clk) (221:221:221))
    )
  )
  (CELL
    (CELLTYPE "maxii_asynch_lcell")
    (INSTANCE cnt\[2\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (892:892:892) (892:892:892))
        (PORT datab (940:940:940) (940:940:940))
        (PORT datac (975:975:975) (975:975:975))
        (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183))
        (IOPATH datab regin (1061:1061:1061) (1061:1061:1061))
        (IOPATH datac regin (804:804:804) (804:804:804))
      )
    )
  )
  (CELL
    (CELLTYPE "maxii_lcell_register")
    (INSTANCE cnt\[2\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2639:2639:2639) (2639:2639:2639))
        (PORT clk (4378:4378:4378) (4378:4378:4378))
        (IOPATH (posedge clk) regout (376:376:376) (376:376:376))
        (IOPATH (posedge aclr) regout (577:577:577) (577:577:577))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (333:333:333))
      (HOLD datain (posedge clk) (221:221:221))
    )
  )
  (CELL
    (CELLTYPE "maxii_io")
    (INSTANCE clkdiv\~I)
    (DELAY
      (ABSOLUTE
        (PORT datain (2148:2148:2148) (2148:2148:2148))
        (IOPATH datain padio (2322:2322:2322) (2322:2322:2322))
      )
    )
  )
)