📄 sram_test_v.sdo

📁 BJ-EPM240V2实验例程以及说明文档实验之十一读写SRAM
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    (INSTANCE cstate\.IDLE.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (959:959:959) (959:959:959))
        (PORT datab (1833:1833:1833) (1833:1833:1833))
        (PORT datac (766:766:766) (766:766:766))
        (PORT datad (2506:2506:2506) (2506:2506:2506))
        (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183))
        (IOPATH datab regin (1061:1061:1061) (1061:1061:1061))
        (IOPATH datac regin (804:804:804) (804:804:804))
        (IOPATH datad regin (591:591:591) (591:591:591))
      )
    )
  )
  (CELL
    (CELLTYPE "maxii_lcell_register")
    (INSTANCE cstate\.IDLE.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (8413:8413:8413) (8413:8413:8413))
        (PORT clk (2185:2185:2185) (2185:2185:2185))
        (IOPATH (posedge clk) regout (376:376:376) (376:376:376))
        (IOPATH (posedge aclr) regout (577:577:577) (577:577:577))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (333:333:333))
      (HOLD datain (posedge clk) (221:221:221))
    )
  )
  (CELL
    (CELLTYPE "maxii_asynch_lcell")
    (INSTANCE cnt\[0\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (1025:1025:1025) (1025:1025:1025))
        (PORT datad (1894:1894:1894) (1894:1894:1894))
        (IOPATH datac regin (804:804:804) (804:804:804))
        (IOPATH datad regin (591:591:591) (591:591:591))
      )
    )
  )
  (CELL
    (CELLTYPE "maxii_lcell_register")
    (INSTANCE cnt\[0\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (8413:8413:8413) (8413:8413:8413))
        (PORT clk (2185:2185:2185) (2185:2185:2185))
        (IOPATH (posedge clk) regout (376:376:376) (376:376:376))
        (IOPATH (posedge aclr) regout (577:577:577) (577:577:577))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (333:333:333))
      (HOLD datain (posedge clk) (221:221:221))
    )
  )
  (CELL
    (CELLTYPE "maxii_asynch_lcell")
    (INSTANCE cnt\[1\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (963:963:963) (963:963:963))
        (PORT datac (1028:1028:1028) (1028:1028:1028))
        (PORT datad (1894:1894:1894) (1894:1894:1894))
        (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183))
        (IOPATH datac regin (804:804:804) (804:804:804))
        (IOPATH datad regin (591:591:591) (591:591:591))
      )
    )
  )
  (CELL
    (CELLTYPE "maxii_lcell_register")
    (INSTANCE cnt\[1\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (8413:8413:8413) (8413:8413:8413))
        (PORT clk (2185:2185:2185) (2185:2185:2185))
        (IOPATH (posedge clk) regout (376:376:376) (376:376:376))
        (IOPATH (posedge aclr) regout (577:577:577) (577:577:577))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (333:333:333))
      (HOLD datain (posedge clk) (221:221:221))
    )
  )
  (CELL
    (CELLTYPE "maxii_asynch_lcell")
    (INSTANCE cstate\.REA0.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (969:969:969) (969:969:969))
        (PORT datab (741:741:741) (741:741:741))
        (PORT datac (950:950:950) (950:950:950))
        (PORT datad (1105:1105:1105) (1105:1105:1105))
        (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183))
        (IOPATH datab regin (1061:1061:1061) (1061:1061:1061))
        (IOPATH datac regin (804:804:804) (804:804:804))
        (IOPATH datad regin (591:591:591) (591:591:591))
      )
    )
  )
  (CELL
    (CELLTYPE "maxii_lcell_register")
    (INSTANCE cstate\.REA0.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (8413:8413:8413) (8413:8413:8413))
        (PORT clk (2185:2185:2185) (2185:2185:2185))
        (IOPATH (posedge clk) regout (376:376:376) (376:376:376))
        (IOPATH (posedge aclr) regout (577:577:577) (577:577:577))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (333:333:333))
      (HOLD datain (posedge clk) (221:221:221))
    )
  )
  (CELL
    (CELLTYPE "maxii_asynch_lcell")
    (INSTANCE cstate\.REA1.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (976:976:976) (976:976:976))
        (PORT datab (1370:1370:1370) (1370:1370:1370))
        (PORT datac (1039:1039:1039) (1039:1039:1039))
        (PORT datad (2013:2013:2013) (2013:2013:2013))
        (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183))
        (IOPATH datab regin (1061:1061:1061) (1061:1061:1061))
        (IOPATH datac regin (804:804:804) (804:804:804))
        (IOPATH datad regin (591:591:591) (591:591:591))
      )
    )
  )
  (CELL
    (CELLTYPE "maxii_lcell_register")
    (INSTANCE cstate\.REA1.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (8413:8413:8413) (8413:8413:8413))
        (PORT clk (2185:2185:2185) (2185:2185:2185))
        (IOPATH (posedge clk) regout (376:376:376) (376:376:376))
        (IOPATH (posedge aclr) regout (577:577:577) (577:577:577))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (333:333:333))
      (HOLD datain (posedge clk) (221:221:221))
    )
  )
  (CELL
    (CELLTYPE "maxii_asynch_lcell")
    (INSTANCE rd_data\[1\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (3393:3393:3393) (3393:3393:3393))
      )
    )
  )
  (CELL
    (CELLTYPE "maxii_lcell_register")
    (INSTANCE rd_data\[1\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT datac (3673:3673:3673) (3673:3673:3673))
        (PORT aclr (8413:8413:8413) (8413:8413:8413))
        (PORT clk (2185:2185:2185) (2185:2185:2185))
        (PORT ena (3067:3067:3067) (3067:3067:3067))
        (IOPATH (posedge clk) regout (376:376:376) (376:376:376))
        (IOPATH (posedge aclr) regout (577:577:577) (577:577:577))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (333:333:333))
      (SETUP datain (posedge clk) (333:333:333))
      (SETUP ena (posedge clk) (333:333:333))
      (HOLD datac (posedge clk) (221:221:221))
      (HOLD datain (posedge clk) (221:221:221))
      (HOLD ena (posedge clk) (221:221:221))
    )
  )
  (CELL
    (CELLTYPE "maxii_asynch_lcell")
    (INSTANCE rd_data\[5\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1322:1322:1322) (1322:1322:1322))
        (PORT datab (1820:1820:1820) (1820:1820:1820))
        (PORT datac (3542:3542:3542) (3542:3542:3542))
        (PORT datad (920:920:920) (920:920:920))
        (IOPATH dataa combout (914:914:914) (914:914:914))
        (IOPATH datab combout (740:740:740) (740:740:740))
        (IOPATH datad combout (200:200:200) (200:200:200))
        (IOPATH qfbkin combout (595:595:595) (595:595:595))
      )
    )
  )
  (CELL
    (CELLTYPE "maxii_lcell_register")
    (INSTANCE rd_data\[5\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT datac (3822:3822:3822) (3822:3822:3822))
        (PORT aclr (8413:8413:8413) (8413:8413:8413))
        (PORT clk (2185:2185:2185) (2185:2185:2185))
        (PORT ena (3067:3067:3067) (3067:3067:3067))
        (IOPATH (posedge clk) qfbkout (376:376:376) (376:376:376))
        (IOPATH (posedge aclr) qfbkout (577:577:577) (577:577:577))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (333:333:333))
      (SETUP datain (posedge clk) (333:333:333))
      (SETUP ena (posedge clk) (333:333:333))
      (HOLD datac (posedge clk) (221:221:221))
      (HOLD datain (posedge clk) (221:221:221))
      (HOLD ena (posedge clk) (221:221:221))
    )
  )
  (CELL
    (CELLTYPE "maxii_asynch_lcell")
    (INSTANCE rd_data\[7\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (2547:2547:2547) (2547:2547:2547))
        (IOPATH datab regin (1061:1061:1061) (1061:1061:1061))
      )
    )
  )
  (CELL
    (CELLTYPE "maxii_lcell_register")
    (INSTANCE rd_data\[7\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (8413:8413:8413) (8413:8413:8413))
        (PORT clk (2185:2185:2185) (2185:2185:2185))
        (PORT ena (3067:3067:3067) (3067:3067:3067))
        (IOPATH (posedge clk) regout (376:376:376) (376:376:376))
        (IOPATH (posedge aclr) regout (577:577:577) (577:577:577))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (333:333:333))
      (SETUP ena (posedge clk) (333:333:333))
      (HOLD datain (posedge clk) (221:221:221))
      (HOLD ena (posedge clk) (221:221:221))
    )
  )
  (CELL
    (CELLTYPE "maxii_asynch_lcell")
    (INSTANCE wr_data\[6\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (893:893:893) (893:893:893))
        (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183))
        (IOPATH cin regin (1367:1367:1367) (1367:1367:1367))
        (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161))
        (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150))
        (IOPATH dataa cout0 (978:978:978) (978:978:978))
        (IOPATH cin0 cout0 (123:123:123) (123:123:123))
        (IOPATH dataa cout1 (973:973:973) (973:973:973))
        (IOPATH cin1 cout1 (111:111:111) (111:111:111))
      )
    )
  )
  (CELL
    (CELLTYPE "maxii_lcell_register")
    (INSTANCE wr_data\[6\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (8413:8413:8413) (8413:8413:8413))
        (PORT clk (2185:2185:2185) (2185:2185:2185))
        (PORT ena (1917:1917:1917) (1917:1917:1917))
        (IOPATH (posedge clk) regout (376:376:376) (376:376:376))
        (IOPATH (posedge aclr) regout (577:577:577) (577:577:577))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (333:333:333))
      (SETUP ena (posedge clk) (333:333:333))
      (HOLD datain (posedge clk) (221:221:221))
      (HOLD ena (posedge clk) (221:221:221))
    )
  )
  (CELL
    (CELLTYPE "maxii_asynch_lcell")
    (INSTANCE wr_data\[7\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (902:902:902) (902:902:902))
        (IOPATH datab regin (1061:1061:1061) (1061:1061:1061))
        (IOPATH cin regin (1367:1367:1367) (1367:1367:1367))
        (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161))
        (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150))
      )
    )
  )
  (CELL
    (CELLTYPE "maxii_lcell_register")
    (INSTANCE wr_data\[7\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (8413:8413:8413) (8413:8413:8413))
        (PORT clk (2185:2185:2185) (2185:2185:2185))
        (PORT ena (1917:1917:1917) (1917:1917:1917))
        (IOPATH (posedge clk) regout (376:376:376) (376:376:376))
        (IOPATH (posedge aclr) regout (577:577:577) (577:577:577))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (333:333:333))
      (SETUP ena (posedge clk) (333:333:333))
      (HOLD datain (posedge clk) (221:221:221))
      (HOLD ena (posedge clk) (221:221:221))
    )
  )
  (CELL
    (CELLTYPE "maxii_asynch_lcell")
    (INSTANCE rd_data\[0\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (896:896:896) (896:896:896))
        (PORT datab (1960:1960:1960) (1960:1960:1960))
        (PORT datac (3454:3454:3454) (3454:3454:3454))
        (PORT datad (2095:2095:2095) (2095:2095:2095))
        (IOPATH dataa combout (914:914:914) (914:914:914))
        (IOPATH datab combout (740:740:740) (740:740:740))
        (IOPATH datad combout (200:200:200) (200:200:200))
        (IOPATH qfbkin combout (595:595:595) (595:595:595))
      )
    )
  )
  (CELL
    (CELLTYPE "maxii_lcell_register")
    (INSTANCE rd_data\[0\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT datac (3734:3734:3734) (3734:3734:3734))
        (PORT aclr (8413:8413:8413) (8413:8413:8413))
        (PORT clk (2185:2185:2185) (2185:2185:2185))
        (PORT ena (3067:3067:3067) (3067:3067:3067))
        (IOPATH (posedge clk) qfbkout (376:376:376) (376:376:376))
        (IOPATH (posedge aclr) qfbkout (577:577:577) (577:577:577))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (333:333:333))
      (SETUP datain (posedge clk) (333:333:333))
      (SETUP ena (posedge clk) (333:333:333))
      (HOLD datac (posedge clk) (221:221:221))
      (HOLD datain (posedge clk) (221:221:221))
      (HOLD ena (posedge clk) (221:221:221))
    )
  )
  (CELL
    (CELLTYPE "maxii_asynch_lcell")
    (INSTANCE rd_data\[3\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (2584:2584:2584) (2584:2584:2584))
        (IOPATH datab regin (1061:1061:1061) (1061:1061:1061))
      )
    )
  )
  (CELL
    (CELLTYPE "maxii_lcell_register")
    (INSTANCE rd_data\[3\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (8413:8413:8413) (8413:8413:8413))
        (PORT clk (2185:2185:2185) (2185:2185:2185))
        (PORT ena (3067:3067:3067) (3067:3067:3067))
        (IOPATH (posedge clk) regout (376:376:376) (376:376:376))
        (IOPATH (posedge aclr) regout (577:577:577) (577:577:577))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (333:333:333))
      (SETUP ena (posedge clk) (333:333:333))
      (HOLD datain (posedge clk) (221:221:221))
      (HOLD ena (pos
上一页 1 2 3 45
💿 文件大小 453 K
👤 上传用户 GUAIGUAICHENGTI
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#BJ-EPM #SRAM #240 #实验
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