aes_cipher_top.v

密钥扩展模块的接口如图4.4。clk为系统时钟

/////////////////////////////////////////////////////////////////////
////                                                             ////
////  AES Cipher Top Level                                       ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          [e-mail]                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/aes_core/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         [e-mail]                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////

//  CVS Log
//
//  $Id: aes_cipher_top.v,v 1.1.1.1 2002/11/09 11:22:48 rudi Exp $
//
//  $Date: 2002/11/09 11:22:48 $
//  $Revision: 1.1.1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: aes_cipher_top.v,v $
//               Revision 1.1.1.1  2002/11/09 11:22:48  rudi
//               Initial Checkin
//
//
//
//
//
//

`include "timescale.v"

module aes_cipher_top(clk, rst, ld, done, key, text_in, text_out );
input		clk, rst;
input		ld;
output		done;
input	[127:0]	key;
input	[127:0]	text_in;
output	[127:0]	text_out;

////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire	[31:0]	w0, w1, w2, w3;

reg	[127:0]	text_in_r;
reg	[127:0]	text_out;
reg	[7:0]	sa00, sa01, sa02, sa03;
reg	[7:0]	sa10, sa11, sa12, sa13;
reg	[7:0]	sa20, sa21, sa22, sa23;
reg	[7:0]	sa30, sa31, sa32, sa33;
wire	[7:0]	sa00_next, sa01_next, sa02_next, sa03_next;
wire	[7:0]	sa10_next, sa11_next, sa12_next, sa13_next;
wire	[7:0]	sa20_next, sa21_next, sa22_next, sa23_next;
wire	[7:0]	sa30_next, sa31_next, sa32_next, sa33_next;

reg	[7:0]	sa00_sr, sa01_sr, sa02_sr, sa03_sr;
reg	[7:0]	sa10_sr, sa11_sr, sa12_sr, sa13_sr;
reg	[7:0]	sa20_sr, sa21_sr, sa22_sr, sa23_sr;
reg	[7:0]	sa30_sr, sa31_sr, sa32_sr, sa33_sr;
wire	[7:0]	sa00_mc, sa01_mc, sa02_mc, sa03_mc;
wire	[7:0]	sa10_mc, sa11_mc, sa12_mc, sa13_mc;
wire	[7:0]	sa20_mc, sa21_mc, sa22_mc, sa23_mc;
wire	[7:0]	sa30_mc, sa31_mc, sa32_mc, sa33_mc;
reg  [7:0] sa0, sa1, sa2, sa3 ;
wire  [7:0] sa0_sub, sa1_sub, sa2_sub, sa3_sub;
reg	[31:0]	w[3:0];
reg	done, ld_r;
reg	[7:0]	dcnt;
reg	[3:0] k;

 

reg	[31:0]	subword;




////////////////////////////////////////////////////////////////////
//
// Misc Logic
//

always @(posedge clk)
	if(!rst)	
	dcnt <= #1 8'h0;

	else
	if(ld)		
	begin	

  	dcnt <= #1 8'h28;
	end

	else
	if(|dcnt)	dcnt <= #1 dcnt - 8'h1;

always @(posedge clk) done <= #1  !(|dcnt[7:1]) & dcnt[0] & !ld;
always @(posedge clk) if(ld) text_in_r <= #1 text_in;
always @(posedge clk) ld_r <= #1 ld;

////////////////////////////////////////////////////////////////////
//
// Initial Permutation (AddRoundKey)
//

always @(posedge clk)
begin
  if (ld_r)
  begin
   sa33 <= #1  text_in_r[007:000] ^ w3[07:00];

   sa23 <= #1  text_in_r[015:008] ^ w3[15:08];

	sa13 <= #1  text_in_r[023:016] ^ w3[23:16]; 
	
   sa03 <= #1  text_in_r[031:024] ^ w3[31:24]; 

	sa32 <= #1  text_in_r[039:032] ^ w2[07:00];

	sa22 <= #1  text_in_r[047:040] ^ w2[15:08];

	sa12 <= #1  text_in_r[055:048] ^ w2[23:16];

	sa02 <= #1  text_in_r[063:056] ^ w2[31:24];

	sa31 <= #1  text_in_r[071:064] ^ w1[07:00]; 

	sa21 <= #1  text_in_r[079:072] ^ w1[15:08]; 

	sa11 <= #1  text_in_r[087:080] ^ w1[23:16];

	sa01 <= #1  text_in_r[095:088] ^ w1[31:24];

	sa30 <= #1  text_in_r[103:096] ^ w0[07:00];

	sa20 <= #1  text_in_r[111:104] ^ w0[15:08]; 

	sa10 <= #1  text_in_r[119:112] ^ w0[23:16];

	sa00 <= #1  text_in_r[127:120] ^ w0[31:24];
	end

	else
	if (k[2]&(!k[1])&(!k[0]))
	begin
	sa33 <= #1  sa33_next;

   sa23 <= #1  sa23_next;

	sa13 <= #1  sa13_next;
	
   sa03 <= #1  sa03_next;

	sa32 <= #1  sa32_next;

	sa22 <= #1  sa22_next;

	sa12 <= #1  sa12_next;

	sa02 <= #1  sa02_next;

	sa31 <= #1  sa31_next;

	sa21 <= #1  sa21_next;

	sa11 <= #1  sa11_next;

	sa01 <= #1  sa01_next;

	sa30 <= #1  sa30_next;

	sa20 <= #1  sa20_next;

	sa10 <= #1  sa10_next;

	sa00 <= #1  sa00_next;
	end
end

////////////////////////////////////////////////////////////////////
//
// Round Permutations
//
always @(posedge clk)

if(!rst)
k <= #1 4'h0;
else

begin
  k <=#1 k+4'h1;
if (k[2]&(!k[1])&!k[0]) k<=4'h0; 
case(k)
  4'h0:
       begin
       {sa0, sa1, sa2, sa3} <=w3;
		 #1 subword <={sa0_sub,sa1_sub, sa2_sub,sa3_sub};
		 end	
  4'h1: 
       begin
       {sa0, sa1, sa2, sa3} <={sa00, sa01, sa02, sa03};
	  	 #1 {sa00_sr,sa01_sr,sa02_sr,sa03_sr} <={sa0_sub,sa1_sub,sa2_sub,sa3_sub};

       end
  4'h2: 
       begin
      {sa0, sa1, sa2, sa3} <={sa10, sa11, sa12, sa13};
		 #1 {sa13_sr,sa10_sr,sa11_sr,sa12_sr} <={sa0_sub,sa1_sub,sa2_sub,sa3_sub};
       end
  4'h3:
       begin
       {sa0, sa1, sa2, sa3} <={sa20, sa21, sa22, sa23};
		 #1 {sa22_sr,sa23_sr,sa20_sr,sa21_sr} <={sa0_sub,sa1_sub,sa2_sub,sa3_sub};
       end
  4'h4:
       begin
       {sa0, sa1, sa2, sa3} <={sa30, sa31, sa32, sa33};
		 #1 {sa31_sr,sa32_sr,sa33_sr,sa30_sr} <={sa0_sub,sa1_sub, sa2_sub,sa3_sub};
       end

	    		  
endcase
end 

aes_key_expand_128 u0(
	.clk(		clk	),
	.kld(		ld	),
	.k  (		k	),
	.key(		key	),
	.subword(subword),
	.wo_0(		w0	),
	.wo_1(		w1	),
	.wo_2(		w2	),
	.wo_3(		w3	));


aes_sbox us0(	.a(	sa0	), .d(	sa0_sub	));
aes_sbox us1(	.a(	sa1	), .d(	sa1_sub	));
aes_sbox us2(	.a(	sa2	), .d(	sa2_sub	));
aes_sbox us3(	.a(	sa3	), .d(	sa3_sub	));	



assign {sa00_mc, sa10_mc, sa20_mc, sa30_mc}  = mix_col(sa00_sr,sa10_sr,sa20_sr,sa30_sr);
assign {sa01_mc, sa11_mc, sa21_mc, sa31_mc}  = mix_col(sa01_sr,sa11_sr,sa21_sr,sa31_sr);
assign {sa02_mc, sa12_mc, sa22_mc, sa32_mc}  = mix_col(sa02_sr,sa12_sr,sa22_sr,sa32_sr);
assign {sa03_mc, sa13_mc, sa23_mc, sa33_mc}  = mix_col(sa03_sr,sa13_sr,sa23_sr,sa33_sr);

assign sa00_next = sa00_mc ^ w0[31:24];
assign sa01_next = sa01_mc ^ w1[31:24];
assign sa02_next = sa02_mc ^ w2[31:24];
assign sa03_next = sa03_mc ^ w3[31:24];
assign sa10_next = sa10_mc ^ w0[23:16];
assign sa11_next = sa11_mc ^ w1[23:16];
assign sa12_next = sa12_mc ^ w2[23:16];
assign sa13_next = sa13_mc ^ w3[23:16];
assign sa20_next = sa20_mc ^ w0[15:08];
assign sa21_next = sa21_mc ^ w1[15:08];
assign sa22_next = sa22_mc ^ w2[15:08];
assign sa23_next = sa23_mc ^ w3[15:08];
assign sa30_next = sa30_mc ^ w0[07:00];
assign sa31_next = sa31_mc ^ w1[07:00];
assign sa32_next = sa32_mc ^ w2[07:00];
assign sa33_next = sa33_mc ^ w3[07:00];

////////////////////////////////////////////////////////////////////
//
// Final text output
//

always @(posedge clk) text_out[127:120] <= #1 sa00_sr ^ w0[31:24];
always @(posedge clk) text_out[095:088] <= #1 sa01_sr ^ w1[31:24];
always @(posedge clk) text_out[063:056] <= #1 sa02_sr ^ w2[31:24];
always @(posedge clk) text_out[031:024] <= #1 sa03_sr ^ w3[31:24];
always @(posedge clk) text_out[119:112] <= #1 sa10_sr ^ w0[23:16];
always @(posedge clk) text_out[087:080] <= #1 sa11_sr ^ w1[23:16];
always @(posedge clk) text_out[055:048] <= #1 sa12_sr ^ w2[23:16];
always @(posedge clk) text_out[023:016] <= #1 sa13_sr ^ w3[23:16];
always @(posedge clk) text_out[111:104] <= #1 sa20_sr ^ w0[15:08];
always @(posedge clk) text_out[079:072] <= #1 sa21_sr ^ w1[15:08];
always @(posedge clk) text_out[047:040] <= #1 sa22_sr ^ w2[15:08];
always @(posedge clk) text_out[015:008] <= #1 sa23_sr ^ w3[15:08];
always @(posedge clk) text_out[103:096] <= #1 sa30_sr ^ w0[07:00];
always @(posedge clk) text_out[071:064] <= #1 sa31_sr ^ w1[07:00];
always @(posedge clk) text_out[039:032] <= #1 sa32_sr ^ w2[07:00];
always @(posedge clk) text_out[007:000] <= #1 sa33_sr ^ w3[07:00];

////////////////////////////////////////////////////////////////////
//
// Generic Functions
//

function [31:0] mix_col;
input	[7:0]	s0,s1,s2,s3;
reg	[7:0]	s0_o,s1_o,s2_o,s3_o;
begin
mix_col[31:24]=xtime(s0)^xtime(s1)^s1^s2^s3;
mix_col[23:16]=s0^xtime(s1)^xtime(s2)^s2^s3;
mix_col[15:08]=s0^s1^xtime(s2)^xtime(s3)^s3;
mix_col[07:00]=xtime(s0)^s0^s1^s2^xtime(s3);
end
endfunction

function [7:0] xtime;
input [7:0] b; xtime={b[6:0],1'b0}^(8'h1b&{8{b[7]}});
endfunction

////////////////////////////////////////////////////////////////////
//
// Modules
//




endmodule