lab3.tan.summary

组合逻辑单元设计电路

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.584 ns
From           : B1[0]
To             : F[2]$latch
From Clock     : --
To Clock       : S2S1S0[2]
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.758 ns
From           : F[3]$latch
To             : F[3]
From Clock     : S2S1S0[0]
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.002 ns
From           : S2S1S0[2]
To             : F[3]$latch
From Clock     : --
To Clock       : S2S1S0[0]
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------