📄 lab3.tan.rpt
字号:
; N/A ; None ; -2.858 ns ; A1[2] ; F[4]$latch ; C0 ;
; N/A ; None ; -2.894 ns ; A1[3] ; F[4]$latch ; C0 ;
; N/A ; None ; -2.912 ns ; A1[1] ; F[4]$latch ; S2S1S0[1] ;
; N/A ; None ; -2.913 ns ; A1[2] ; F[3]$latch ; C0 ;
; N/A ; None ; -2.967 ns ; A1[1] ; F[3]$latch ; S2S1S0[1] ;
; N/A ; None ; -2.969 ns ; C0 ; F[4]$latch ; S2S1S0[1] ;
; N/A ; None ; -2.988 ns ; A1[0] ; F[1]$latch ; S2S1S0[2] ;
; N/A ; None ; -3.000 ns ; B1[3] ; F[4]$latch ; S2S1S0[1] ;
; N/A ; None ; -3.023 ns ; A1[1] ; F[4]$latch ; C0 ;
; N/A ; None ; -3.024 ns ; C0 ; F[3]$latch ; S2S1S0[1] ;
; N/A ; None ; -3.071 ns ; A1[2] ; F[4]$latch ; S2S1S0[2] ;
; N/A ; None ; -3.078 ns ; A1[1] ; F[3]$latch ; C0 ;
; N/A ; None ; -3.080 ns ; C0 ; F[4]$latch ; C0 ;
; N/A ; None ; -3.107 ns ; A1[3] ; F[4]$latch ; S2S1S0[2] ;
; N/A ; None ; -3.111 ns ; B1[3] ; F[4]$latch ; C0 ;
; N/A ; None ; -3.116 ns ; A1[1] ; F[2]$latch ; S2S1S0[0] ;
; N/A ; None ; -3.126 ns ; A1[2] ; F[3]$latch ; S2S1S0[2] ;
; N/A ; None ; -3.135 ns ; C0 ; F[3]$latch ; C0 ;
; N/A ; None ; -3.171 ns ; C0 ; F[2]$latch ; S2S1S0[0] ;
; N/A ; None ; -3.175 ns ; B1[1] ; F[4]$latch ; S2S1S0[1] ;
; N/A ; None ; -3.186 ns ; B1[0] ; F[1]$latch ; S2S1S0[1] ;
; N/A ; None ; -3.218 ns ; A1[0] ; F[4]$latch ; S2S1S0[1] ;
; N/A ; None ; -3.230 ns ; B1[1] ; F[3]$latch ; S2S1S0[1] ;
; N/A ; None ; -3.236 ns ; A1[1] ; F[4]$latch ; S2S1S0[2] ;
; N/A ; None ; -3.251 ns ; B1[2] ; F[4]$latch ; S2S1S0[1] ;
; N/A ; None ; -3.255 ns ; B1[0] ; F[4]$latch ; S2S1S0[0] ;
; N/A ; None ; -3.273 ns ; A1[0] ; F[3]$latch ; S2S1S0[1] ;
; N/A ; None ; -3.286 ns ; B1[1] ; F[4]$latch ; C0 ;
; N/A ; None ; -3.291 ns ; A1[1] ; F[3]$latch ; S2S1S0[2] ;
; N/A ; None ; -3.293 ns ; C0 ; F[4]$latch ; S2S1S0[2] ;
; N/A ; None ; -3.297 ns ; B1[0] ; F[1]$latch ; C0 ;
; N/A ; None ; -3.306 ns ; B1[2] ; F[3]$latch ; S2S1S0[1] ;
; N/A ; None ; -3.310 ns ; B1[0] ; F[3]$latch ; S2S1S0[0] ;
; N/A ; None ; -3.324 ns ; B1[3] ; F[4]$latch ; S2S1S0[2] ;
; N/A ; None ; -3.329 ns ; A1[0] ; F[4]$latch ; C0 ;
; N/A ; None ; -3.341 ns ; B1[1] ; F[3]$latch ; C0 ;
; N/A ; None ; -3.348 ns ; C0 ; F[3]$latch ; S2S1S0[2] ;
; N/A ; None ; -3.362 ns ; B1[2] ; F[4]$latch ; C0 ;
; N/A ; None ; -3.381 ns ; B1[1] ; F[2]$latch ; S2S1S0[0] ;
; N/A ; None ; -3.384 ns ; A1[0] ; F[3]$latch ; C0 ;
; N/A ; None ; -3.417 ns ; B1[2] ; F[3]$latch ; C0 ;
; N/A ; None ; -3.420 ns ; A1[0] ; F[2]$latch ; S2S1S0[0] ;
; N/A ; None ; -3.499 ns ; B1[1] ; F[4]$latch ; S2S1S0[2] ;
; N/A ; None ; -3.510 ns ; B1[0] ; F[1]$latch ; S2S1S0[2] ;
; N/A ; None ; -3.542 ns ; A1[0] ; F[4]$latch ; S2S1S0[2] ;
; N/A ; None ; -3.554 ns ; B1[1] ; F[3]$latch ; S2S1S0[2] ;
; N/A ; None ; -3.575 ns ; B1[2] ; F[4]$latch ; S2S1S0[2] ;
; N/A ; None ; -3.597 ns ; A1[0] ; F[3]$latch ; S2S1S0[2] ;
; N/A ; None ; -3.599 ns ; A1[1] ; F[2]$latch ; S2S1S0[1] ;
; N/A ; None ; -3.630 ns ; B1[2] ; F[3]$latch ; S2S1S0[2] ;
; N/A ; None ; -3.654 ns ; C0 ; F[2]$latch ; S2S1S0[1] ;
; N/A ; None ; -3.710 ns ; A1[1] ; F[2]$latch ; C0 ;
; N/A ; None ; -3.738 ns ; B1[0] ; F[4]$latch ; S2S1S0[1] ;
; N/A ; None ; -3.765 ns ; C0 ; F[2]$latch ; C0 ;
; N/A ; None ; -3.793 ns ; B1[0] ; F[3]$latch ; S2S1S0[1] ;
; N/A ; None ; -3.849 ns ; B1[0] ; F[4]$latch ; C0 ;
; N/A ; None ; -3.864 ns ; B1[1] ; F[2]$latch ; S2S1S0[1] ;
; N/A ; None ; -3.903 ns ; A1[0] ; F[2]$latch ; S2S1S0[1] ;
; N/A ; None ; -3.904 ns ; B1[0] ; F[3]$latch ; C0 ;
; N/A ; None ; -3.923 ns ; A1[1] ; F[2]$latch ; S2S1S0[2] ;
; N/A ; None ; -3.942 ns ; B1[0] ; F[2]$latch ; S2S1S0[0] ;
; N/A ; None ; -3.975 ns ; B1[1] ; F[2]$latch ; C0 ;
; N/A ; None ; -3.978 ns ; C0 ; F[2]$latch ; S2S1S0[2] ;
; N/A ; None ; -4.014 ns ; A1[0] ; F[2]$latch ; C0 ;
; N/A ; None ; -4.062 ns ; B1[0] ; F[4]$latch ; S2S1S0[2] ;
; N/A ; None ; -4.117 ns ; B1[0] ; F[3]$latch ; S2S1S0[2] ;
; N/A ; None ; -4.188 ns ; B1[1] ; F[2]$latch ; S2S1S0[2] ;
; N/A ; None ; -4.227 ns ; A1[0] ; F[2]$latch ; S2S1S0[2] ;
; N/A ; None ; -4.425 ns ; B1[0] ; F[2]$latch ; S2S1S0[1] ;
; N/A ; None ; -4.536 ns ; B1[0] ; F[2]$latch ; C0 ;
; N/A ; None ; -4.749 ns ; B1[0] ; F[2]$latch ; S2S1S0[2] ;
+---------------+-------------+-----------+-----------+------------+-----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Mon May 04 15:05:45 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lab3 -c lab3 --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
Warning: Node "F[0]$latch" is a latch
Warning: Node "F[1]$latch" is a latch
Warning: Node "F[2]$latch" is a latch
Warning: Node "F[3]$latch" is a latch
Warning: Node "F[4]$latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "S2S1S0[2]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Info: Assuming node "C0" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Info: Assuming node "S2S1S0[1]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Info: Assuming node "S2S1S0[0]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected gated clock "Mux5~9" as buffer
Info: tsu for register "F[2]$latch" (data pin = "B1[0]", clock pin = "S2S1S0[2]") is 5.584 ns
Info: + Longest pin to register delay is 12.763 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_5; Fanout = 2; PIN Node = 'B1[0]'
Info: 2: + IC(5.963 ns) + CELL(0.292 ns) = 7.724 ns; Loc. = LC_X4_Y4_N4; Fanout = 3; COMB Node = 'Add0~470'
Info: 3: + IC(0.680 ns) + CELL(0.432 ns) = 8.836 ns; Loc. = LC_X3_Y4_N2; Fanout = 2; COMB Node = 'Add0~456COUT1'
Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 8.916 ns; Loc. = LC_X3_Y4_N3; Fanout = 2; COMB Node = 'Add0~459COUT1'
Info: 5: + IC(0.000 ns) + CELL(0.608 ns) = 9.524 ns; Loc. = LC_X3_Y4_N4; Fanout = 1; COMB Node = 'Add0~461'
Info: 6: + IC(0.678 ns) + CELL(0.442 ns) = 10.644 ns; Loc. = LC_X4_Y4_N9; Fanout = 1; COMB Node = 'Add0~463'
Info: 7: + IC(1.529 ns) + CELL(0.590 ns) = 12.763 ns; Loc. = LC_X8_Y2_N3; Fanout = 1; REG Node = 'F[2]$latch'
Info: Total cell delay = 3.913 ns ( 30.66 % )
Info: Total interconnect delay = 8.850 ns ( 69.34 % )
Info: + Micro setup delay of destination is 0.820 ns
Info: - Shortest clock path from clock "S2S1S0[2]" to destination register is 7.999 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_38; Fanout = 7; CLK Node = 'S2S1S0[2]'
Info: 2: + IC(1.299 ns) + CELL(0.114 ns) = 2.888 ns; Loc. = LC_X3_Y4_N7; Fanout = 5; COMB Node = 'Mux5~9'
Info: 3: + IC(4.819 ns) + CELL(0.292 ns) = 7.999 ns; Loc. = LC_X8_Y2_N3; Fanout = 1; REG Node = 'F[2]$latch'
Info: Total cell delay = 1.881 ns ( 23.52 % )
Info: Total interconnect delay = 6.118 ns ( 76.48 % )
Info: tco from clock "S2S1S0[0]" to destination pin "F[3]" through register "F[3]$latch" is 12.758 ns
Info: + Longest clock path from clock "S2S1S0[0]" to source register is 8.602 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_36; Fanout = 13; CLK Node = 'S2S1S0[0]'
Info: 2: + IC(1.636 ns) + CELL(0.590 ns) = 3.695 ns; Loc. = LC_X3_Y4_N7; Fanout = 5; COMB Node = 'Mux5~9'
Info: 3: + IC(4.793 ns) + CELL(0.114 ns) = 8.602 ns; Loc. = LC_X1_Y4_N5; Fanout = 1; REG Node = 'F[3]$latch'
Info: Total cell delay = 2.173 ns ( 25.26 % )
Info: Total interconnect delay = 6.429 ns ( 74.74 % )
Info: + Micro clock to output delay of source is 0.000 ns
Info: + Longest register to pin delay is 4.156 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y4_N5; Fanout = 1; REG Node = 'F[3]$latch'
Info: 2: + IC(2.048 ns) + CELL(2.108 ns) = 4.156 ns; Loc. = PIN_49; Fanout = 0; PIN Node = 'F[3]'
Info: Total cell delay = 2.108 ns ( 50.72 % )
Info: Total interconnect delay = 2.048 ns ( 49.28 % )
Info: th for register "F[3]$latch" (data pin = "S2S1S0[2]", clock pin = "S2S1S0[0]") is 1.002 ns
Info: + Longest clock path from clock "S2S1S0[0]" to destination register is 8.602 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_36; Fanout = 13; CLK Node = 'S2S1S0[0]'
Info: 2: + IC(1.636 ns) + CELL(0.590 ns) = 3.695 ns; Loc. = LC_X3_Y4_N7; Fanout = 5; COMB Node = 'Mux5~9'
Info: 3: + IC(4.793 ns) + CELL(0.114 ns) = 8.602 ns; Loc. = LC_X1_Y4_N5; Fanout = 1; REG Node = 'F[3]$latch'
Info: Total cell delay = 2.173 ns ( 25.26 % )
Info: Total interconnect delay = 6.429 ns ( 74.74 % )
Info: + Micro hold delay of destination is 0.000 ns
Info: - Shortest pin to register delay is 7.600 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_38; Fanout = 7; CLK Node = 'S2S1S0[2]'
Info: 2: + IC(5.102 ns) + CELL(0.292 ns) = 6.869 ns; Loc. = LC_X1_Y4_N2; Fanout = 1; COMB Node = 'Add0~466'
Info: 3: + IC(0.439 ns) + CELL(0.292 ns) = 7.600 ns; Loc. = LC_X1_Y4_N5; Fanout = 1; REG Node = 'F[3]$latch'
Info: Total cell delay = 2.059 ns ( 27.09 % )
Info: Total interconnect delay = 5.541 ns ( 72.91 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 8 warnings
Info: Allocated 110 megabytes of memory during processing
Info: Processing ended: Mon May 04 15:05:46 2009
Info: Elapsed time: 00:00:01
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