prev_cmp_lab3.tan.qmsg

组合逻辑单元设计电路

{ "Info" "ITDB_TSU_RESULT" "F\[2\]\$latch B1\[0\] S2S1S0\[2\] 5.584 ns register " "Info: tsu for register \"F\[2\]\$latch\" (data pin = \"B1\[0\]\", clock pin = \"S2S1S0\[2\]\") is 5.584 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.763 ns + Longest pin register " "Info: + Longest pin to register delay is 12.763 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns B1\[0\] 1 PIN PIN_5 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_5; Fanout = 2; PIN Node = 'B1\[0\]'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "" { B1[0] } "NODE_NAME" } } { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.963 ns) + CELL(0.292 ns) 7.724 ns Add0~470 2 COMB LC_X4_Y4_N4 3 " "Info: 2: + IC(5.963 ns) + CELL(0.292 ns) = 7.724 ns; Loc. = LC_X4_Y4_N4; Fanout = 3; COMB Node = 'Add0~470'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "6.255 ns" { B1[0] Add0~470 } "NODE_NAME" } } { "g:/quartus7.20/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus7.20/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.680 ns) + CELL(0.432 ns) 8.836 ns Add0~456COUT1 3 COMB LC_X3_Y4_N2 2 " "Info: 3: + IC(0.680 ns) + CELL(0.432 ns) = 8.836 ns; Loc. = LC_X3_Y4_N2; Fanout = 2; COMB Node = 'Add0~456COUT1'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "1.112 ns" { Add0~470 Add0~456COUT1 } "NODE_NAME" } } { "g:/quartus7.20/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus7.20/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 8.916 ns Add0~459COUT1 4 COMB LC_X3_Y4_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 8.916 ns; Loc. = LC_X3_Y4_N3; Fanout = 2; COMB Node = 'Add0~459COUT1'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add0~456COUT1 Add0~459COUT1 } "NODE_NAME" } } { "g:/quartus7.20/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus7.20/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 9.524 ns Add0~461 5 COMB LC_X3_Y4_N4 1 " "Info: 5: + IC(0.000 ns) + CELL(0.608 ns) = 9.524 ns; Loc. = LC_X3_Y4_N4; Fanout = 1; COMB Node = 'Add0~461'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { Add0~459COUT1 Add0~461 } "NODE_NAME" } } { "g:/quartus7.20/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus7.20/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.678 ns) + CELL(0.442 ns) 10.644 ns Add0~463 6 COMB LC_X4_Y4_N9 1 " "Info: 6: + IC(0.678 ns) + CELL(0.442 ns) = 10.644 ns; Loc. = LC_X4_Y4_N9; Fanout = 1; COMB Node = 'Add0~463'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "1.120 ns" { Add0~461 Add0~463 } "NODE_NAME" } } { "g:/quartus7.20/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus7.20/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.529 ns) + CELL(0.590 ns) 12.763 ns F\[2\]\$latch 7 REG LC_X8_Y2_N3 1 " "Info: 7: + IC(1.529 ns) + CELL(0.590 ns) = 12.763 ns; Loc. = LC_X8_Y2_N3; Fanout = 1; REG Node = 'F\[2\]\$latch'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "2.119 ns" { Add0~463 F[2]$latch } "NODE_NAME" } } { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.913 ns ( 30.66 % ) " "Info: Total cell delay = 3.913 ns ( 30.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.850 ns ( 69.34 % ) " "Info: Total interconnect delay = 8.850 ns ( 69.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "12.763 ns" { B1[0] Add0~470 Add0~456COUT1 Add0~459COUT1 Add0~461 Add0~463 F[2]$latch } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "12.763 ns" { B1[0] {} B1[0]~out0 {} Add0~470 {} Add0~456COUT1 {} Add0~459COUT1 {} Add0~461 {} Add0~463 {} F[2]$latch {} } { 0.000ns 0.000ns 5.963ns 0.680ns 0.000ns 0.000ns 0.678ns 1.529ns } { 0.000ns 1.469ns 0.292ns 0.432ns 0.080ns 0.608ns 0.442ns 0.590ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.820 ns + " "Info: + Micro setup delay of destination is 0.820 ns" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "S2S1S0\[2\] destination 7.999 ns - Shortest register " "Info: - Shortest clock path from clock \"S2S1S0\[2\]\" to destination register is 7.999 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns S2S1S0\[2\] 1 CLK PIN_38 7 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_38; Fanout = 7; CLK Node = 'S2S1S0\[2\]'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "" { S2S1S0[2] } "NODE_NAME" } } { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.299 ns) + CELL(0.114 ns) 2.888 ns Mux5~9 2 COMB LC_X3_Y4_N7 5 " "Info: 2: + IC(1.299 ns) + CELL(0.114 ns) = 2.888 ns; Loc. = LC_X3_Y4_N7; Fanout = 5; COMB Node = 'Mux5~9'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "1.413 ns" { S2S1S0[2] Mux5~9 } "NODE_NAME" } } { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.819 ns) + CELL(0.292 ns) 7.999 ns F\[2\]\$latch 3 REG LC_X8_Y2_N3 1 " "Info: 3: + IC(4.819 ns) + CELL(0.292 ns) = 7.999 ns; Loc. = LC_X8_Y2_N3; Fanout = 1; REG Node = 'F\[2\]\$latch'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "5.111 ns" { Mux5~9 F[2]$latch } "NODE_NAME" } } { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.881 ns ( 23.52 % ) " "Info: Total cell delay = 1.881 ns ( 23.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.118 ns ( 76.48 % ) " "Info: Total interconnect delay = 6.118 ns ( 76.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "7.999 ns" { S2S1S0[2] Mux5~9 F[2]$latch } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "7.999 ns" { S2S1S0[2] {} S2S1S0[2]~out0 {} Mux5~9 {} F[2]$latch {} } { 0.000ns 0.000ns 1.299ns 4.819ns } { 0.000ns 1.475ns 0.114ns 0.292ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "12.763 ns" { B1[0] Add0~470 Add0~456COUT1 Add0~459COUT1 Add0~461 Add0~463 F[2]$latch } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "12.763 ns" { B1[0] {} B1[0]~out0 {} Add0~470 {} Add0~456COUT1 {} Add0~459COUT1 {} Add0~461 {} Add0~463 {} F[2]$latch {} } { 0.000ns 0.000ns 5.963ns 0.680ns 0.000ns 0.000ns 0.678ns 1.529ns } { 0.000ns 1.469ns 0.292ns 0.432ns 0.080ns 0.608ns 0.442ns 0.590ns } "" } } { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "7.999 ns" { S2S1S0[2] Mux5~9 F[2]$latch } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "7.999 ns" { S2S1S0[2] {} S2S1S0[2]~out0 {} Mux5~9 {} F[2]$latch {} } { 0.000ns 0.000ns 1.299ns 4.819ns } { 0.000ns 1.475ns 0.114ns 0.292ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "S2S1S0\[0\] F\[3\] F\[3\]\$latch 12.758 ns register " "Info: tco from clock \"S2S1S0\[0\]\" to destination pin \"F\[3\]\" through register \"F\[3\]\$latch\" is 12.758 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "S2S1S0\[0\] source 8.602 ns + Longest register " "Info: + Longest clock path from clock \"S2S1S0\[0\]\" to source register is 8.602 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns S2S1S0\[0\] 1 CLK PIN_36 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_36; Fanout = 13; CLK Node = 'S2S1S0\[0\]'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "" { S2S1S0[0] } "NODE_NAME" } } { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.636 ns) + CELL(0.590 ns) 3.695 ns Mux5~9 2 COMB LC_X3_Y4_N7 5 " "Info: 2: + IC(1.636 ns) + CELL(0.590 ns) = 3.695 ns; Loc. = LC_X3_Y4_N7; Fanout = 5; COMB Node = 'Mux5~9'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "2.226 ns" { S2S1S0[0] Mux5~9 } "NODE_NAME" } } { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.793 ns) + CELL(0.114 ns) 8.602 ns F\[3\]\$latch 3 REG LC_X1_Y4_N5 1 " "Info: 3: + IC(4.793 ns) + CELL(0.114 ns) = 8.602 ns; Loc. = LC_X1_Y4_N5; Fanout = 1; REG Node = 'F\[3\]\$latch'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "4.907 ns" { Mux5~9 F[3]$latch } "NODE_NAME" } } { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.173 ns ( 25.26 % ) " "Info: Total cell delay = 2.173 ns ( 25.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.429 ns ( 74.74 % ) " "Info: Total interconnect delay = 6.429 ns ( 74.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "8.602 ns" { S2S1S0[0] Mux5~9 F[3]$latch } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "8.602 ns" { S2S1S0[0] {} S2S1S0[0]~out0 {} Mux5~9 {} F[3]$latch {} } { 0.000ns 0.000ns 1.636ns 4.793ns } { 0.000ns 1.469ns 0.590ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.156 ns + Longest register pin " "Info: + Longest register to pin delay is 4.156 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns F\[3\]\$latch 1 REG LC_X1_Y4_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y4_N5; Fanout = 1; REG Node = 'F\[3\]\$latch'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "" { F[3]$latch } "NODE_NAME" } } { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.048 ns) + CELL(2.108 ns) 4.156 ns F\[3\] 2 PIN PIN_49 0 " "Info: 2: + IC(2.048 ns) + CELL(2.108 ns) = 4.156 ns; Loc. = PIN_49; Fanout = 0; PIN Node = 'F\[3\]'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "4.156 ns" { F[3]$latch F[3] } "NODE_NAME" } } { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 50.72 % ) " "Info: Total cell delay = 2.108 ns ( 50.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.048 ns ( 49.28 % ) " "Info: Total interconnect delay = 2.048 ns ( 49.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "4.156 ns" { F[3]$latch F[3] } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "4.156 ns" { F[3]$latch {} F[3] {} } { 0.000ns 2.048ns } { 0.000ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "8.602 ns" { S2S1S0[0] Mux5~9 F[3]$latch } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "8.602 ns" { S2S1S0[0] {} S2S1S0[0]~out0 {} Mux5~9 {} F[3]$latch {} } { 0.000ns 0.000ns 1.636ns 4.793ns } { 0.000ns 1.469ns 0.590ns 0.114ns } "" } } { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "4.156 ns" { F[3]$latch F[3] } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "4.156 ns" { F[3]$latch {} F[3] {} } { 0.000ns 2.048ns } { 0.000ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "F\[3\]\$latch S2S1S0\[2\] S2S1S0\[0\] 1.002 ns register " "Info: th for register \"F\[3\]\$latch\" (data pin = \"S2S1S0\[2\]\", clock pin = \"S2S1S0\[0\]\") is 1.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "S2S1S0\[0\] destination 8.602 ns + Longest register " "Info: + Longest clock path from clock \"S2S1S0\[0\]\" to destination register is 8.602 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns S2S1S0\[0\] 1 CLK PIN_36 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_36; Fanout = 13; CLK Node = 'S2S1S0\[0\]'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "" { S2S1S0[0] } "NODE_NAME" } } { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.636 ns) + CELL(0.590 ns) 3.695 ns Mux5~9 2 COMB LC_X3_Y4_N7 5 " "Info: 2: + IC(1.636 ns) + CELL(0.590 ns) = 3.695 ns; Loc. = LC_X3_Y4_N7; Fanout = 5; COMB Node = 'Mux5~9'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "2.226 ns" { S2S1S0[0] Mux5~9 } "NODE_NAME" } } { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.793 ns) + CELL(0.114 ns) 8.602 ns F\[3\]\$latch 3 REG LC_X1_Y4_N5 1 " "Info: 3: + IC(4.793 ns) + CELL(0.114 ns) = 8.602 ns; Loc. = LC_X1_Y4_N5; Fanout = 1; REG Node = 'F\[3\]\$latch'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "4.907 ns" { Mux5~9 F[3]$latch } "NODE_NAME" } } { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.173 ns ( 25.26 % ) " "Info: Total cell delay = 2.173 ns ( 25.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.429 ns ( 74.74 % ) " "Info: Total interconnect delay = 6.429 ns ( 74.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "8.602 ns" { S2S1S0[0] Mux5~9 F[3]$latch } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "8.602 ns" { S2S1S0[0] {} S2S1S0[0]~out0 {} Mux5~9 {} F[3]$latch {} } { 0.000ns 0.000ns 1.636ns 4.793ns } { 0.000ns 1.469ns 0.590ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.600 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns S2S1S0\[2\] 1 CLK PIN_38 7 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_38; Fanout = 7; CLK Node = 'S2S1S0\[2\]'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "" { S2S1S0[2] } "NODE_NAME" } } { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.102 ns) + CELL(0.292 ns) 6.869 ns Add0~466 2 COMB LC_X1_Y4_N2 1 " "Info: 2: + IC(5.102 ns) + CELL(0.292 ns) = 6.869 ns; Loc. = LC_X1_Y4_N2; Fanout = 1; COMB Node = 'Add0~466'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "5.394 ns" { S2S1S0[2] Add0~466 } "NODE_NAME" } } { "g:/quartus7.20/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus7.20/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.439 ns) + CELL(0.292 ns) 7.600 ns F\[3\]\$latch 3 REG LC_X1_Y4_N5 1 " "Info: 3: + IC(0.439 ns) + CELL(0.292 ns) = 7.600 ns; Loc. = LC_X1_Y4_N5; Fanout = 1; REG Node = 'F\[3\]\$latch'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "0.731 ns" { Add0~466 F[3]$latch } "NODE_NAME" } } { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.059 ns ( 27.09 % ) " "Info: Total cell delay = 2.059 ns ( 27.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.541 ns ( 72.91 % ) " "Info: Total interconnect delay = 5.541 ns ( 72.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "7.600 ns" { S2S1S0[2] Add0~466 F[3]$latch } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "7.600 ns" { S2S1S0[2] {} S2S1S0[2]~out0 {} Add0~466 {} F[3]$latch {} } { 0.000ns 0.000ns 5.102ns 0.439ns } { 0.000ns 1.475ns 0.292ns 0.292ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "8.602 ns" { S2S1S0[0] Mux5~9 F[3]$latch } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "8.602 ns" { S2S1S0[0] {} S2S1S0[0]~out0 {} Mux5~9 {} F[3]$latch {} } { 0.000ns 0.000ns 1.636ns 4.793ns } { 0.000ns 1.469ns 0.590ns 0.114ns } "" } } { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "7.600 ns" { S2S1S0[2] Add0~466 F[3]$latch } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "7.600 ns" { S2S1S0[2] {} S2S1S0[2]~out0 {} Add0~466 {} F[3]$latch {} } { 0.000ns 0.000ns 5.102ns 0.439ns } { 0.000ns 1.475ns 0.292ns 0.292ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 8 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "110 " "Info: Allocated 110 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 14:43:50 2009 " "Info: Processing ended: Mon May 04 14:43:50 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}