prev_cmp_lab3.tan.qmsg

组合逻辑单元设计电路

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 04 14:43:50 2009 " "Info: Processing started: Mon May 04 14:43:50 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off lab3 -c lab3 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lab3 -c lab3 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "F\[0\]\$latch " "Warning: Node \"F\[0\]\$latch\" is a latch" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "F\[1\]\$latch " "Warning: Node \"F\[1\]\$latch\" is a latch" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "F\[2\]\$latch " "Warning: Node \"F\[2\]\$latch\" is a latch" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "F\[3\]\$latch " "Warning: Node \"F\[3\]\$latch\" is a latch" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "F\[4\]\$latch " "Warning: Node \"F\[4\]\$latch\" is a latch" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "S2S1S0\[2\] " "Info: Assuming node \"S2S1S0\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 5 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "C0 " "Info: Assuming node \"C0\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 8 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "S2S1S0\[1\] " "Info: Assuming node \"S2S1S0\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 5 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "S2S1S0\[0\] " "Info: Assuming node \"S2S1S0\[0\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 5 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "Mux5~9 " "Info: Detected gated clock \"Mux5~9\" as buffer" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 19 -1 0 } } { "g:/quartus7.20/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/quartus7.20/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux5~9" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}