lab3.hier_info

组合逻辑单元设计电路

|lab3
S2S1S0[0] => Mux5.IN9
S2S1S0[0] => Mux4.IN10
S2S1S0[0] => Mux3.IN10
S2S1S0[0] => Mux2.IN10
S2S1S0[0] => Mux1.IN10
S2S1S0[0] => Mux0.IN10
S2S1S0[1] => Mux5.IN8
S2S1S0[1] => Mux4.IN9
S2S1S0[1] => Mux3.IN9
S2S1S0[1] => Mux2.IN9
S2S1S0[1] => Mux1.IN9
S2S1S0[1] => Mux0.IN9
S2S1S0[2] => Mux5.IN7
S2S1S0[2] => Mux4.IN8
S2S1S0[2] => Mux3.IN8
S2S1S0[2] => Mux2.IN8
S2S1S0[2] => Mux1.IN8
S2S1S0[2] => Mux0.IN8
A1[0] => F~8.IN0
A1[0] => F~4.IN0
A1[0] => F~0.IN0
A1[0] => Add5.IN10
A1[0] => Add4.IN10
A1[0] => Add2.IN10
A1[0] => Add0.IN6
A1[0] => Mux0.IN7
A1[1] => F~9.IN0
A1[1] => F~5.IN0
A1[1] => F~1.IN0
A1[1] => Add5.IN9
A1[1] => Add4.IN9
A1[1] => Add2.IN9
A1[1] => Add0.IN5
A1[1] => Mux1.IN7
A1[2] => F~10.IN0
A1[2] => F~6.IN0
A1[2] => F~2.IN0
A1[2] => Add5.IN8
A1[2] => Add4.IN8
A1[2] => Add2.IN8
A1[2] => Add0.IN4
A1[2] => Mux2.IN7
A1[3] => F~11.IN0
A1[3] => F~7.IN0
A1[3] => F~3.IN0
A1[3] => Add5.IN7
A1[3] => Add4.IN7
A1[3] => Add2.IN7
A1[3] => Add0.IN3
A1[3] => Mux3.IN7
B1[0] => F~8.IN1
B1[0] => F~4.IN1
B1[0] => F~0.IN1
B1[0] => Add0.IN10
B1[0] => Add2.IN6
B1[1] => F~9.IN1
B1[1] => F~5.IN1
B1[1] => F~1.IN1
B1[1] => Add0.IN9
B1[1] => Add2.IN5
B1[2] => F~10.IN1
B1[2] => F~6.IN1
B1[2] => F~2.IN1
B1[2] => Add0.IN8
B1[2] => Add2.IN4
B1[3] => F~11.IN1
B1[3] => F~7.IN1
B1[3] => F~3.IN1
B1[3] => Add0.IN7
B1[3] => Add2.IN3
C0 => Mux5.IN10
C0 => Add1.IN10
C0 => Add3.IN10
C0 => Mux5.IN6
F[0] <= F[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
F[1] <= F[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
F[2] <= F[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
F[3] <= F[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
F[4] <= F[4]$latch.DB_MAX_OUTPUT_PORT_TYPE