prev_cmp_lab3.map.qmsg

组合逻辑单元设计电路

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "B lab3.vhd(29) " "Warning (10492): VHDL Process Statement warning at lab3.vhd(29): signal \"B\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "A lab3.vhd(30) " "Warning (10492): VHDL Process Statement warning at lab3.vhd(30): signal \"A\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "B lab3.vhd(30) " "Warning (10492): VHDL Process Statement warning at lab3.vhd(30): signal \"B\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "A lab3.vhd(31) " "Warning (10492): VHDL Process Statement warning at lab3.vhd(31): signal \"A\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "F lab3.vhd(17) " "Warning (10631): VHDL Process Statement warning at lab3.vhd(17): inferring latch(es) for signal or variable \"F\", which holds its previous value in one or more paths through the process" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "F\[0\] lab3.vhd(17) " "Info (10041): Inferred latch for \"F\[0\]\" at lab3.vhd(17)" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "F\[1\] lab3.vhd(17) " "Info (10041): Inferred latch for \"F\[1\]\" at lab3.vhd(17)" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "F\[2\] lab3.vhd(17) " "Info (10041): Inferred latch for \"F\[2\]\" at lab3.vhd(17)" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "F\[3\] lab3.vhd(17) " "Info (10041): Inferred latch for \"F\[3\]\" at lab3.vhd(17)" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "F\[4\] lab3.vhd(17) " "Info (10041): Inferred latch for \"F\[4\]\" at lab3.vhd(17)" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "F\[0\]\$latch " "Warning: Latch F\[0\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA S2S1S0\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal S2S1S0\[2\]" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 5 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "F\[1\]\$latch " "Warning: Latch F\[1\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA S2S1S0\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal S2S1S0\[2\]" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 5 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "F\[2\]\$latch " "Warning: Latch F\[2\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA S2S1S0\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal S2S1S0\[2\]" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 5 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "F\[3\]\$latch " "Warning: Latch F\[3\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA S2S1S0\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal S2S1S0\[2\]" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 5 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "F\[4\]\$latch " "Warning: Latch F\[4\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA S2S1S0\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal S2S1S0\[2\]" {  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 5 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "lab3.vhd" "" { Text "G:/EDA实验/实验3/lab3.vhd" 17 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "45 " "Info: Implemented 45 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "28 " "Info: Implemented 28 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 28 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 28 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "157 " "Info: Allocated 157 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 14:43:37 2009 " "Info: Processing ended: Mon May 04 14:43:37 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}