lab2.tan.qmsg

用FPGA做数码管编码器！只有用到7段

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 20 17:55:54 2009 " "Info: Processing started: Mon Apr 20 17:55:54 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off lab2 -c lab2 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lab2 -c lab2 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[1\] b\[1\] 13.365 ns Longest " "Info: Longest tpd from source pin \"a\[1\]\" to destination pin \"b\[1\]\" is 13.365 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns a\[1\] 1 PIN PIN_2 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 7; PIN Node = 'a\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[1] } "NODE_NAME" } } { "实验2/lab2.vhd" "" { Text "F:/0600840129/实验2/lab2.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.613 ns) + CELL(0.590 ns) 9.672 ns Mux5~3 2 COMB LC_X26_Y11_N5 1 " "Info: 2: + IC(7.613 ns) + CELL(0.590 ns) = 9.672 ns; Loc. = LC_X26_Y11_N5; Fanout = 1; COMB Node = 'Mux5~3'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.203 ns" { a[1] Mux5~3 } "NODE_NAME" } } { "实验2/lab2.vhd" "" { Text "F:/0600840129/实验2/lab2.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.569 ns) + CELL(2.124 ns) 13.365 ns b\[1\] 3 PIN PIN_96 0 " "Info: 3: + IC(1.569 ns) + CELL(2.124 ns) = 13.365 ns; Loc. = PIN_96; Fanout = 0; PIN Node = 'b\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.693 ns" { Mux5~3 b[1] } "NODE_NAME" } } { "实验2/lab2.vhd" "" { Text "F:/0600840129/实验2/lab2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.183 ns ( 31.30 % ) " "Info: Total cell delay = 4.183 ns ( 31.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.182 ns ( 68.70 % ) " "Info: Total interconnect delay = 9.182 ns ( 68.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "13.365 ns" { a[1] Mux5~3 b[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "13.365 ns" { a[1] a[1]~out0 Mux5~3 b[1] } { 0.000ns 0.000ns 7.613ns 1.569ns } { 0.000ns 1.469ns 0.590ns 2.124ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "106 " "Info: Allocated 106 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 20 17:55:55 2009 " "Info: Processing ended: Mon Apr 20 17:55:55 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}