lab2.vhd.bak

用FPGA做数码管编码器！只有用到7段

library ieee;
use ieee.std_logic_1164.all;
entity lab2 is
port(a:in std_logic_vector(3 downto 0 );
	b:out std_logic_vector(6 downto 0) );
end entity lab2;
architecture a of lab2 is
begin 
 process(a)
 begin
 case a is
  when "0000" => b<="0111111";
  when "0001" => b<="0000110";
  when "0010" => b<="1011011";
  when "0011" => b<="1001111";
  when "0100" => b<="1100110";
  when "0101" => b<="1101101";
  when "0110" => b<="1111101";
  when "0111" => b<="0000111";
  when "1000" => b<="1111111";
  when "1001" => b<="1101111";
  when "1010" => b<="1110111";
  when "1011" => b<="1111100";
  when "1100" => b<="0111001";
  when "1101" => b<="1011110";
  when "1110" => b<="1111001";
  when "1111" => b<="1110001";
  when others => null;
end case;
end process;
end;