ext_mem_to_link_tx.asm

TS101 DMA演示程序,包括链路口DMA,二维DMA

/***********************************************************************************************************
		Example code showing the DMA transfer from internal memory to external SDRAM and then from
		the external memory to the link ports. The data is then received back in through the link port
		and stored to internal memory. The receiving processor receives the data in through the link port
		and transfers it directly to external SDRAM.

		The example reads the data file tx_data.dat as the original data to be transferred via the first DMA.
		
************************************************************************************************************/
#define N 64
.extern sdram_data;

.section data1;
.align 4;
.var 	data_tx[N] = "tx_data.dat";	
.var	link_data_rx[N];



.section reset;
/************************* Disable all DMA's, Link Ports and Vector Interrupts************************/
	XR0 = 0x00000000;;		// DMA source/destination
	XR1 = 0x00000000;;		// count =4, modify = 4
	XR2 = 0x00000000;;		// Y count/modify
	XR3 = 0x00000000;;		// TCB DP register
	LCTL0 = xr0;;			// disable link ports
	LCTL1 = xr0;;			// disable link ports
	LCTL2 = xr0;;			// disable link ports
	LCTL3 = xr0;;			// disable link ports
	DCS0 = XR3:0;;			// disable external port 0 DMA
	DCS1 = XR3:0;;			// disable external port 1 DMA
	DCS2 = XR3:0;;			// disable external port 2 DMA
	DCS3 = XR3:0;;			// disable external port 3 DMA
	DCD0 = XR3:0;;			// disable external port 0 DMA
	DCD1 = XR3:0;;			// disable external port 1 DMA
	DCD2 = XR3:0;;			// disable external port 2 DMA
	DCD3 = XR3:0;;			// disable external port 3 DMA
	DC4 = XR3:0;;			// disable link 0 tx DMA
	DC5 = XR3:0;;			// disable link 1 tx DMA
	DC6 = XR3:0;;			// disable link 2 tx DMA
	DC7 = XR3:0;;			// disable link 3 tx DMA
	DC8 = XR3:0;;			// disable link 0 rx DMA
	DC9 = XR3:0;;			// disable link 1 rx DMA
	DC10 = XR3:0;;			// disable link 2 rx DMA
	DC11 = XR3:0;;			// disable link 3 rx DMA

	xr0 = 0x90010000;;
	xr1 = 0x00000000;;
	IMASKH = xr0;;			// enable emulation debug, Global enable HW interrupts and enable vector interrupts
	IMASKL = xr1;;			// disable all interrupt vector DMA channels until required
/************************************************************************/


/************************* System Control and SDRAM setup ************************/
	/* Setting Up of Control Registers */

	j14 = j31 + 0x3879e7;;				
	SYSCON = j14;;						// 0000000000 1 1 1 0 0 00 11 1 1 00 11 1 1 00 11 1
										// |RESERVED| | | | | |  |  | | |  |  | | |  |  | |
										//			  | | | | |  |  | | |  |  | | |  |  | Bank 0 idle
										//			  | | | | |  |  | | |  |  | | |  |  Bank 0 Internal wait
										//			  | | | | |  |  | | |  |  | | |  Bank 0 Pipe depth
										//			  | | | | |  |  | | |  |  | | Bank 0 Slow
  									    //			  | | | | |  |  | | |  |  | Bank 1 idle
   										//			  | | | | |  |  | | |  |  Bank 1 Internal wait
										//			  | | | | |  |  | | |  Bank 1 Pipe depth
										//			  | | | | |  |  | | Bank 1 Slow
										//			  | | | | |  |  | Host idle
										//			  | | | | |  |  Host Internal wait
										//			  | | | | |  Host Pipe depth  
										//			  | | | | Host Slow 
										//			  | | | Not used
  									    //			  | | Bus width Memory
 									    //			  | Bus width Multiprocessor
										//            Bus width Host
   	

	j11 = j31 + 0x00005B05;;					
	SDRCON = j11;;  					// 00000000000000000 1 011 01 10 0 00 0 10 1
										// |---RESERVED----| |  |   |  | |  | |  | |
										//					 |  |   |  | |  | |  | SDRAM Enabled
										//					 |  |   |  | |  | |  CAS Latency = 3 cycles
										//					 |  |   |  | |  | Pipe Depth = 0 cycles
										//					 |  |   |  | |  Page Boundary = 256 Words
										//					 |  |   |  | Reserved
										//					 |  |   |  Refresh Rate = every 1200 cycles
										//					 |  |   Precharge to RAS Delay = three cycles
										//					 |  RAS to Precharge Delay = 5 cycles
										//					 Init Sequence refresh then MRS
/************************************************************************/
	xr0 = IMASKL;;						 
	xr1 = 0x40804000;;
	xr0 = r0 or r1;;
	IMASKL = xr0;;						// enable DMA0, DMA5 & DMA 9 interrupts---External port 0 & Link port 1 Tx & Rx

	j0 = j31 + _dma_int;;				// set DMA interrupt vector
	IVDMA0 = j0;;		
	IVDMA5 = j0;;
	IVDMA9 = j0;;
		
	xr4 = N;;							// Count value
	xr5 = lshift r4 by 16;;				// Shift count value so ready to be ORed with modify value				
	xr6 = 4;;							// Modify value
	xr0 = data_tx;;						// xr0 = destination index
	xr1 = r6 or r5;;					// 0000000001000000 0000000000000100
										// |--------------| |--------------|
										//		  |                 |
										//	      |					Modify Value
										//		  Number of normal words to be transferred
									
	xr6 = 0x00000000;;					// Not a 2 dimensional array so value does not matter
	xr3 = 0x47000000;;					// 010 0 0 11 1 0 0 00000 00 000000000000000
										//  |  | |  | | | |   |    |        |
										//  |  | |  | | | |   |    |        Chain Pointer Quad Word Address
										//  |  | |  | | | |   |    Memory select for chain pointer
										//  |  | |  | | | |   Chaining Destination Channel
										//  |  | |  | | | Chaining Enabled (disabled)
										//  |  | |  | | DMA Request Enable (0=once DMA channel is enabled entire block is transferred)
										//  |  | |  | Interrupt Enable (enabled)
										//  |  | |  Operand Length 00=Reserved, 01=Normal word, 10=Long word, 11=Quad word
										//  |  | Two Dimensional DMA (disabled)
										//  |  Determines Priority 0=DMA request priority normal 1=high
										//  Specify Device Type (010=Internal memory)

	xr8 = sdram_data;;					// Destination Index
	xr9 = xr1;;							// Count and Modify for TCB
	xr11 = 0x87000000;;					// DP register setup. Same as above except external memory selected

	DCS0 = xr3:0;;						// Load source TCB
	DCD0 = xr11:8;;						// Load destination TCB
	idle;;								// once DMA is completed an interrupt is generated which brings out of idle and jumps to _dma_int
	xr0 = 0x000004DA;;					// 00000000000000000000 0 1 0 0 1 1 011 0 1 0
										// |-----RESERVED-----| | | | | | |  |  | | |
										// 					    | | | | | |  |  | | RESERVED
										// 					    | | | | | |  |  | Direction Enable (enabled)
										//					    | | | | | |  |  Verification Enable (disabled)
										//					    | | | | | |  SPD Transfer speed 000=CCLK/8, 001=CCLK/4, 010=CCLK/3, 011=CCLK/2
										//					    | | | | | Transmit Enable (enabled)
										//					    | | | | Packet Size 0=64 quads in one packet, 1=Indefinite number of bytes in one packet
										//					    | | | Transmit Time Out Check Enable (disabled)
										//					    | | Connectivity Error Check Enable (disabled)
										//					    | Receive Enable (enabled)
										//					    Receive Time Out Check Enable
	
	LCTL1 = xr0;;
	DC5 = xr11:8;;						// Load Link Port 1 TCB

	idle;;

	xr8 = link_data_rx;;				// xr4 = destination index
	xr11 = 0x47000000;;
	DC9 = xr11:8;;						// start Link1 receive DMA						
	idle;;								// once DMA is completed an interrupt is generated which brings out of idle and jumps to _dma_int



_end_loop:
	jump _end_loop;nop;nop;nop;;

_dma_int:								// Once tx and rx DMA's are completed an interrupt is generated. This is the isr
	nop;;
	nop;;
	nop;;
	rti(ABS);nop;nop;nop;;