ext_mem_to_link_tx.c

TS101 DMA演示程序,包括链路口DMA,二维DMA

/***********************************************************************************************************
		Example code showing the DMA transfer from internal memory to external SDRAM and then from
		the external memory to the link ports. The data is then received back in through the link port
		and stored to internal memory. The receiving processor receives the data in through the link port
		and transfers it directly to external SDRAM.

		The example reads the data file tx_data.dat as the original data to be transferred via the first DMA.
		
************************************************************************************************************/
#define __NOUNDERSCORES__							// Depending on the compiler patch installed, the register names as defined in sysreg.h 
													// may now have two underscores prepended so that they do not restrict the namespace 
													// of user programs. If the old names are required as in this example(without the 
													// underscores prepended), 
													// define the preprocessor macro __NOUNDERSCORES__ before including sysreg.h.
													// Only required with compiler patch 6.1.7 or later

#include "sysreg.h"
#include "signal.h"
#include "stdio.h"

#define N 64										// Number of words to transfer

extern int sdram_data[N];
int dm data_tx[N] = {								// Data to be transmitted to external memory
#include "tx_data.dat"
};

int dm link_data_rx[N];									// Data received back from receiving processor memory

struct TCB {
	int *DI;										// index
	int DX;											// count and stride in x direction
	int DY;											// count and stride in y direction
	int DP;											// DMA control word
};

struct TCB TCB_temp;								// Temp structure for programming TCBs

__builtin_quad q;									// Temp quad for programming TCBs

void dma0_int();										// Prototype for interrupt service routine
void dma5_int();
void dma9_int();

void main(void)
{
	int i=0;	
	__builtin_sysreg_write(SYSCON,0x003879E7);		// 64-bit external bus for memory (MBUB)
	__builtin_sysreg_write(SDRCON,0x00005B05);		// SDRAM enabled, CAS LATENCY = three, Pipe Depth = 0, Page Boundry = 256,
													// Refresh Rate = 1200, PRC to RAS DELAY = 3, RAS TO PRC DELAY = 5,
													// INIT Sequence = REFRESH then MRS(MBUB)
	
	interrupt(SIGDMA0, dma0_int);					// Assign isr to DMA channel 0
													
	TCB_temp.DI = data_tx;							// index points to source buffer
	TCB_temp.DX = 4 | (N << 16);					// modify is 4 for quad-word transfers, count is N and must be shifted to upper half 
	TCB_temp.DY = 0;								// only a 1 dimension DMA
	TCB_temp.DP = 0x47000000;						// control word set for quad-word transfers to internal memory with interrupt enabled

	q = __builtin_compose_128((long long)TCB_temp.DI | (long long)TCB_temp.DX << 32, (long long)(TCB_temp.DY | (long long)TCB_temp.DP << 32));
	__builtin_sysreg_write4(DCS0, q);				// program the TCBs

	TCB_temp.DI = sdram_data;						// index points to buffer in SDRAM
	TCB_temp.DP = 0x87000000;						// control word set for quad-word transfers to external memory with interrupt enabled

	q = __builtin_compose_128((long long)TCB_temp.DI | (long long)TCB_temp.DX << 32, (long long)(TCB_temp.DY | (long long)TCB_temp.DP << 32));
	__builtin_sysreg_write4(DCD0, q);				// program the TCBs


	while(1)										// Endless loop
		i=i-i;
}


/*********************************************************************************************************************************************/
/*	DMA0 Interrupt Service Routine ***********************************************************************************************************/
/*********************************************************************************************************************************************/
void dma0_int()										// ISR for DMA channel 0
{		
	interrupt(SIGDMA5, dma5_int);					// Assign isr to DMA channel 5
	
	TCB_temp.DI = sdram_data;						// index points to source buffer in external memory
	TCB_temp.DP = 0x87000000;						// control word set for quad-word transfers to external memory with interrupt enabled

	__builtin_sysreg_write(LCTL1,0x000004DA);

	q = __builtin_compose_128((long long)TCB_temp.DI | (long long)TCB_temp.DX << 32, (long long)(TCB_temp.DY | (long long)TCB_temp.DP << 32));
	__builtin_sysreg_write4(DC5, q);				// program the TCBs
	
return;
}

/*********************************************************************************************************************************************/
/*	DMA5 Interrupt Service Routine ***********************************************************************************************************/
/*********************************************************************************************************************************************/
void dma5_int()										// ISR for DMA channel 5
{		
	interrupt(SIGDMA9, dma9_int);					// Assign isr to DMA channel 9
	
	TCB_temp.DI = link_data_rx;						// index points to source buffer in external memory
	TCB_temp.DP = 0x47000000;						// control word set for quad-word transfers to external memory with interrupt enabled

	__builtin_sysreg_write(LCTL1,0x000004DA);

	q = __builtin_compose_128((long long)TCB_temp.DI | (long long)TCB_temp.DX << 32, (long long)(TCB_temp.DY | (long long)TCB_temp.DP << 32));
	__builtin_sysreg_write4(DC9, q);				// program the TCBs
	
	return;	
}


/*********************************************************************************************************************************************/
/*	DMA9 Interrupt Service Routine ***********************************************************************************************************/
/*********************************************************************************************************************************************/
void dma9_int()										// ISR for DMA channel 9
{		

printf("\nAll DMAs to and from external memory and link ports completed\n"); 
	return;
}