2_dimensional_dma.asm

TS101 DMA演示程序,包括链路口DMA,二维DMA

/*****************************************************************************************************
		Example code showing a 2 dimensional DMA transfer from internal memory to external SDRAM and 
		then back from SDRAM to internal memory again. Two DMA channels are used, DMA0 and DMA1.
		The example reads the data file tx_data.dat as the data to be transmitted.
		
******************************************************************************************************/
#define N 64
#define XCOUNT 8
#define YCOUNT 8

.section data1;
.align 4;
.var 	data_tx[N] = "tx_data.dat";	
.var	data_rx[N];

.section ext_data;
.var	sdram_data[N];


.section reset;
/************************* Disable all DMA's and Vector Interrupts************************/
	XR0 = 0x00000000;;		// DMA source/destination
	XR1 = 0x00040004;;		// count =4, modify = 4
	XR2 = 0x00000000;;		// Y count/modify
	XR3 = 0x00000000;;		// TCB DP register
	DCS0 = XR3:0;;			// disable external port 0 DMA
	DCS1 = XR3:0;;			// disable external port 1 DMA
	DCS2 = XR3:0;;			// disable external port 2 DMA
	DCS3 = XR3:0;;			// disable external port 3 DMA
	DCD0 = XR3:0;;			// disable external port 0 DMA
	DCD1 = XR3:0;;			// disable external port 1 DMA
	DCD2 = XR3:0;;			// disable external port 2 DMA
	DCD3 = XR3:0;;			// disable external port 3 DMA
	DC4 = XR3:0;;			// disable link 0 tx DMA
	DC5 = XR3:0;;			// disable link 1 tx DMA
	DC6 = XR3:0;;			// disable link 2 tx DMA
	DC7 = XR3:0;;			// disable link 3 tx DMA
	DC8 = XR3:0;;			// disable link 0 rx DMA
	DC9 = XR3:0;;			// disable link 1 rx DMA
	DC10 = XR3:0;;			// disable link 2 rx DMA
	DC11 = XR3:0;;			// disable link 3 rx DMA

	xr0 = 0x90010000;;
	xr1 = 0x00000000;;
	IMASKH = xr0;;			// enable emulation debug, Global enable HW interrupts and enable vector interrupts
	IMASKL = xr1;;			// disable all interrupt vector DMA channels until required
/************************************************************************/


/************************* System Control and SDRAM setup ************************/
	/* Setting Up of Control Registers */

	j14 = j31 + 0x3879e7;;				
	SYSCON = j14;;						// 0000000000 1 1 1 0 0 00 11 1 1 00 11 1 1 00 11 1
										// |RESERVED| | | | | |  |  | | |  |  | | |  |  | |
										//			  | | | | |  |  | | |  |  | | |  |  | Bank 0 idle
										//			  | | | | |  |  | | |  |  | | |  |  Bank 0 Internal wait
										//			  | | | | |  |  | | |  |  | | |  Bank 0 Pipe depth
										//			  | | | | |  |  | | |  |  | | Bank 0 Slow
  									    //			  | | | | |  |  | | |  |  | Bank 1 idle
   										//			  | | | | |  |  | | |  |  Bank 1 Internal wait
										//			  | | | | |  |  | | |  Bank 1 Pipe depth
										//			  | | | | |  |  | | Bank 1 Slow
										//			  | | | | |  |  | Host idle
										//			  | | | | |  |  Host Internal wait
										//			  | | | | |  Host Pipe depth  
										//			  | | | | Host Slow 
										//			  | | | Not used
  									    //			  | | Bus width Memory
 									    //			  | Bus width Multiprocessor
										//            Bus width Host
   	

	j11 = j31 + 0x00005B05;;					
	SDRCON = j11;;  					// 00000000000000000 1 011 01 10 0 00 0 10 1
										// |---RESERVED----| |  |   |  | |  | |  | |
										//					 |  |   |  | |  | |  | SDRAM Enabled
										//					 |  |   |  | |  | |  CAS Latency = 3 cycles
										//					 |  |   |  | |  | Pipe Depth = 0 cycles
										//					 |  |   |  | |  Page Boundary = 256 Words
										//					 |  |   |  | Reserved
										//					 |  |   |  Refresh Rate = every 1200 cycles
										//					 |  |   Precharge to RAS Delay = three cycles
										//					 |  RAS to Precharge Delay = 5 cycles
										//					 Init Sequence refresh then MRS
/************************************************************************/


	xr0 = IMASKL;;						 
	xr1 = 0x0000C000;;
	j0 = j31 + _dma_int;;				// set DMA interrupt vector
	xr0 = r0 or r1;;
	IVDMA0 = j0;;		
	IVDMA1 = j0;;
	IMASKL = xr0;;						// enable DMA0 & DMA1 interrupts---External ports 0 & 1
		
	xr4 = XCOUNT;;						// Count value
	xr6 = 4;;							// Modify value
	xr5 = lshift r4 by 16;;				// Shift count value so ready to be ORed with modify value				
	xr0 = data_tx;;						// xr0 = destination index
	xr1 = r6 or r5;;					// 0000000000001000 0000000000000100
										// |--------------| |--------------|
										//		  |                 |
										//	      |					Modify Value
										//		  Number of normal words to be transferred in X dimension
									
	xr3 = 0x4F000000;;					// 010 0 1 11 1 0 0 00000 00 000000000000000
										//  |  | |  | | | |   |    |        |
										//  |  | |  | | | |   |    |        Chain Pointer Quad Word Address
										//  |  | |  | | | |   |    Memory select for chain pointer
										//  |  | |  | | | |   Chaining Destination Channel
										//  |  | |  | | | Chaining Enabled (disabled)
										//  |  | |  | | DMA Request Enable (0=once DMA channel is enabled entire block is transferred)
										//  |  | |  | Interrupt Enable (enabled)
										//  |  | |  Operand Length 00=Reserved, 01=Normal word, 10=Long word, 11=Quad word
										//  |  | Two Dimensional DMA (disabled)
										//  |  Determines Priority 0=DMA request priority normal 1=high
										//  Specify Device Type (010=Internal memory)
	xr4 = YCOUNT;;
	xr6 = 4;;
	xr5 = lshift r4 by 16;;								
	xr2 = r6 or r5;;					// 0000000000001000 0000000000000100
										// |--------------| |--------------|
										//		  |                 |
										//	      |					Modify Value
										//		  Number of normal words to be transferred in Y dimension
	

	xr8 = sdram_data;;					// Destination Index
	xr9 = xr1;;							// Count and Modify for TCB
	xr10= xr2;;
	xr11 = 0x8F000000;;					// DP register setup. Same as above except external memory selected

	DCS0 = xr3:0;;						// Load source TCB
	DCD0 = xr11:8;;						// Load destination TCB
	idle;;								// once DMA is completed an interrupt is generated which brings out of idle and jumps to _dma_int
	xr0 = data_rx;;						// Destination index
	DCS1 = xr11:8;;						// Load source TCB
	DCD1 = xr3:0;;						// Load destination TCB
	idle;;

_end_loop:
	jump _end_loop;nop;nop;nop;;

_dma_int:								// Once tx and rx DMA's are completed an interrupt is generated. Next two lines are then executed
	nop;;
	nop;;
	nop;;
	rti(ABS);nop;nop;nop;;