adsp-ts101_mp_asm.ldf

TS101 DMA演示程序,包括链路口DMA,二维DMA

ARCHITECTURE(ADSP-TS101)

SEARCH_DIR( $ADI_DSP\TS\lib )

// Libraries from the command line are included in COMMAND_LINE_OBJECTS.
$OBJECTS = $COMMAND_LINE_OBJECTS;

// Internal memory blocks are 0x10000 (64k)


MEMORY
{
   	M0Code	{ TYPE(RAM) START(0x00000000) END(0x0000FFFF) WIDTH(32) }
    M1Data	{ TYPE(RAM) START(0x00080000) END(0x0008FFFF) WIDTH(32) }
    M2Data	{ TYPE(RAM) START(0x00100000) END(0x0010FFFF) WIDTH(32) }
	SDRAM   { TYPE(RAM) START(0x04000000) END(0x07FFFFFF) WIDTH(32) }
	MS0     { TYPE(RAM) START(0x08000000) END(0x0BFFFFFF) WIDTH(32) }
    MS1     { TYPE(RAM) START(0x0C000000) END(0x0FFFFFFF) WIDTH(32) }
       // Memory blocks need to be less than 2 Gig.
    HOST        { TYPE(RAM) START(0x10000000) END(0x2FFFFFFF) WIDTH(32) }
    HOST1       { TYPE(RAM) START(0x30000000) END(0x4FFFFFFF) WIDTH(32) }
    HOST2       { TYPE(RAM) START(0x50000000) END(0x6FFFFFFF) WIDTH(32) }
    HOST3       { TYPE(RAM) START(0x70000000) END(0x8FFFFFFF) WIDTH(32) }
    HOST4       { TYPE(RAM) START(0x90000000) END(0xAFFFFFFF) WIDTH(32) }
    HOST5       { TYPE(RAM) START(0xB0000000) END(0xCFFFFFFF) WIDTH(32) }
    HOST6       { TYPE(RAM) START(0xD0000000) END(0xEFFFFFFF) WIDTH(32) }
    HOST7       { TYPE(RAM) START(0xF0000000) END(0xFFFFFFFF) WIDTH(32) }
}


// Offset value for each DSP - Corresponds to each DSP's address in the MMS //
MPMEMORY
{
	p0 { START(0x02000000) }			// Offset value for DSP with ID_0
	p1 { START(0x02400000) }			// Offset value for DSP with ID_1
}


PROCESSOR p0
{
  
	OUTPUT(chained_tx.dxe)					 // Executable generated for DSP_0

    SECTIONS
    {
	    code
        {
            FILL(0xb3c00000)
			INPUT_SECTION_ALIGN(4)	  
			INPUT_SECTIONS( chained_tx.doj(program))
        } >M0Code
    
		
		data1
        {
               
            INPUT_SECTIONS( chained_tx.doj(data1))
        } >M1Data

        
        data2
        {
            INPUT_SECTIONS( chained_tx.doj(data2))
        } >M2Data

		external_memory
        {
            INPUT_SECTIONS( chained_tx.doj(ext_data))
        } >SDRAM

	}
}

PROCESSOR p1
{
  
	OUTPUT( chained_rx.dxe)					 // Executable generated for DSP_1

    SECTIONS
    {
	    code
        {
            FILL(0xb3c00000)
			INPUT_SECTION_ALIGN(4)	  
			INPUT_SECTIONS( chained_rx.doj(program))
        } >M0Code
    
		
		data1
        {
               
            INPUT_SECTIONS( chained_rx.doj(data1))
        } >M1Data

        
        data2
        {
            INPUT_SECTIONS( chained_rx.doj(data2))
        } >M2Data

	}
}