chained_tx.asm

TS101 DMA演示程序,包括链路口DMA,二维DMA

/*****************************************************************************************************
		Example code showing the use of DMA chaining.

		The chain consists of 4 transfers. The first transfer is from internal memory to SDRAM on DMA
		channel 0. The second consists of half the data transfered to SDRAM being transferred back to 
		internal memory	from SDRAM using DMA channel 1. The third transfer is the transfer of the second
		half of the data in external memory being transfered to link port 1 on DMA channel 5. The receiver
		stores the data in internal memory and then transmits it back out through link port 0. The fourth
		transfer consists of the data being read from linkport 1 and stored to internal memory with the
		use of DMA channel 9.		
******************************************************************************************************/
#define N 64
.section data1;
.align 4;
.var 	data_tx[N] = "tx_data.dat";	
.var	data_rx[N];

.section data2;
.align 4;
.var 	TCB_int_source[4] = data_tx, 0x00400004, 0x00000000, (0x46450000+0x2);			   // 010 0 0 11 1 0 1 00010 10 000000000000010
.var	TCB_ext_dest[4] = sdram_data, 0x00400004, 0x00000000, (0x86470000+0x3);			   // 100 0 0 11 1 0 1 00011 10 000000000000011
.var	TCB_ext_source[4] = sdram_data, 0x00200004, 0x00000000, (0x86530000+0x4);		   // 100 0 0 11 1 0 1 01001 10 000000000000100
.var	TCB_int_dest[4] = data_rx, 0x00200004, 0x00000000, (0x46400000+0x0);			   // 010 0 0 11 1 0 1 00000 00 000000000000000
.var	TCB_link_tx[4] = (sdram_data+0x20), 0x00200004, 0x00000000, (0x86630000+0x5);      // 100 0 0 11 1 0 1 10001 10 000000000000101
.var	TCB_link_rx[4] = (data_rx+0x20), 0x00200004, 0x00000000, (0x47000000+0x0);	       // 010 0 0 11 1 0 0 00000 00 000000000000000
																						   //  |  | |  | | | |   |    |        |
																						   //  |  | |  | | | |   |    |        Chain Pointer Quad Word Address
																						   //  |  | |  | | | |   |    Memory select for chain pointer
																						   //  |  | |  | | | |   Chaining Destination Channel
																						   //  |  | |  | | | Chaining Enabled (enabled)
																						   //  |  | |  | | DMA Request Enable (0=once DMA channel is enabled entire block is transferred)
																						   //  |  | |  | Interrupt Enable (enabled)
																						   //  |  | |  Operand Length 00=Reserved, 01=Normal word, 10=Long word, 11=Quad word
																						   //  |  | Two Dimensional DMA (disabled)
																						   //  |  Determines Priority 0=DMA request priority normal 1=high
																						   //  Specify Device Type (010=Internal memory)

.section ext_data;
.var	sdram_data[N];


.section program;
/************************* Disable all DMA's and Vector Interrupts************************/
	XR0 = 0x00000000;;		// DMA source/destination
	XR1 = 0x00040004;;		// count =4, modify = 4
	XR2 = 0x00000000;;		// Y count/modify
	XR3 = 0x00000000;;		// TCB DP register
	DCS0 = XR3:0;;			// disable external port 0 DMA
	DCS1 = XR3:0;;			// disable external port 1 DMA
	DCS2 = XR3:0;;			// disable external port 2 DMA
	DCS3 = XR3:0;;			// disable external port 3 DMA
	DCD0 = XR3:0;;			// disable external port 0 DMA
	DCD1 = XR3:0;;			// disable external port 1 DMA
	DCD2 = XR3:0;;			// disable external port 2 DMA
	DCD3 = XR3:0;;			// disable external port 3 DMA
	DC4 = XR3:0;;			// disable link 0 tx DMA
	DC5 = XR3:0;;			// disable link 1 tx DMA
	DC6 = XR3:0;;			// disable link 2 tx DMA
	DC7 = XR3:0;;			// disable link 3 tx DMA
	DC8 = XR3:0;;			// disable link 0 rx DMA
	DC9 = XR3:0;;			// disable link 1 rx DMA
	DC10 = XR3:0;;			// disable link 2 rx DMA
	DC11 = XR3:0;;			// disable link 3 rx DMA

	xr0 = 0x90010000;;
	xr1 = 0x00000000;;
	IMASKH = xr0;;			// enable emulation debug, Global enable HW interrupts and enable vector interrupts
	IMASKL = xr1;;			// disable all interrupt vector DMA channels until required
/************************************************************************/


/************************* System Control and SDRAM setup ************************/
	/* Setting Up of Control Registers */

	j14 = j31 + 0x3879e7;;				
	SYSCON = j14;;						// 0000000000 1 1 1 0 0 00 11 1 1 00 11 1 1 00 11 1
										// |RESERVED| | | | | |  |  | | |  |  | | |  |  | |
										//			  | | | | |  |  | | |  |  | | |  |  | Bank 0 idle
										//			  | | | | |  |  | | |  |  | | |  |  Bank 0 Internal wait
										//			  | | | | |  |  | | |  |  | | |  Bank 0 Pipe depth
										//			  | | | | |  |  | | |  |  | | Bank 0 Slow
  									    //			  | | | | |  |  | | |  |  | Bank 1 idle
   										//			  | | | | |  |  | | |  |  Bank 1 Internal wait
										//			  | | | | |  |  | | |  Bank 1 Pipe depth
										//			  | | | | |  |  | | Bank 1 Slow
										//			  | | | | |  |  | Host idle
										//			  | | | | |  |  Host Internal wait
										//			  | | | | |  Host Pipe depth  
										//			  | | | | Host Slow 
										//			  | | | Not used
  									    //			  | | Bus width Memory
 									    //			  | Bus width Multiprocessor
										//            Bus width Host
   	

	j11 = j31 + 0x00005B05;;					
	SDRCON = j11;;  					// 00000000000000000 1 011 01 10 0 00 0 10 1
										// |---RESERVED----| |  |   |  | |  | |  | |
										//					 |  |   |  | |  | |  | SDRAM Enabled
										//					 |  |   |  | |  | |  CAS Latency = 3 cycles
										//					 |  |   |  | |  | Pipe Depth = 0 cycles
										//					 |  |   |  | |  Page Boundary = 256 Words
										//					 |  |   |  | Reserved
										//					 |  |   |  Refresh Rate = every 1200 cycles
										//					 |  |   Precharge to RAS Delay = three cycles
										//					 |  RAS to Precharge Delay = 5 cycles
										//					 Init Sequence refresh then MRS
/************************************************************************/

xr0 = IMASKL;;						 
	xr1 = 0x4080C000;;
	xr0 = r0 or r1;;
	IMASKL = xr0;;						// enable Link port 1 tx and rx interrupts

	j0 = j31 + _dma_int;;				// set DMA interrupt vector
	IVDMA5 = j0;;
	IVDMA9 = j0;;
	IVDMA0 = j0;;
	IVDMA1 = j0;;	
	xr0 = 0x000004DA;;					// 00000000000000000000 0 1 0 0 1 1 011 0 1 0
										// |-----RESERVED-----| | | | | | |  |  | | |
										// 					    | | | | | |  |  | | RESERVED
										// 					    | | | | | |  |  | Direction Enable (enabled)
										//					    | | | | | |  |  Verification Enable (disabled)
										//					    | | | | | |  SPD Transfer speed 000=CCLK/8, 001=CCLK/4, 010=CCLK/3, 011=CCLK/2
										//					    | | | | | Transmit Enable (enabled)
										//					    | | | | Packet Size 0=64 quads in one packet, 1=Indefinite number of bytes in one packet
										//					    | | | Transmit Time Out Check Enable (disabled)
										//					    | | Connectivity Error Check Enable (disabled)
										//					    | Receive Enable (enabled)
										//					    Receive Time Out Check Enable

	j0 = TCB_int_source;;				// Pointer to source TCB
	j1 = TCB_ext_dest;;					// Pointer to destination TCB
	xr7:4 = Q[j0+=0];;					// Load 4 TCB words to X registers
	xr11:8 = Q[j1+=0];;					// Load 4 TCB words to X registers
	LCTL1 = xr0;;						// Set up link ports
	DCS0 = xr7:4;;						// Load source TCB
	DCD0 = xr11:8;;						// Load destination TCB...this kicks off the chain process
	idle;;								

_end_loop:
	jump _end_loop;nop;nop;nop;;

_dma_int:								// Once link port tx and rx DMA's are completed an interrupt is generated. This is the isr
	nop;;
	nop;;
	nop;;
	rti(ABS);nop;nop;nop;;