chained_tx.c

TS101 DMA演示程序,包括链路口DMA,二维DMA

/*****************************************************************************************************
		Example code showing the use of DMA chaining.

		The chain consists of 4 transfers. The first transfer is from internal memory to SDRAM on DMA
		channel 0. The second consists of half the data transfered to SDRAM being transferred back to 
		internal memory	from SDRAM using DMA channel 1. The third transfer is the transfer of the second
		half of the data in external memory being transfered to link port 1 on DMA channel 5. The receiver
		stores the data in internal memory and then transmits it back out through link port 0. The fourth
		transfer consists of the data being read from linkport 1 and stored to internal memory with the
		use of DMA channel 9.		
******************************************************************************************************/
#define __NOUNDERSCORES__							// Depending on the compiler patch installed, the register names as defined in sysreg.h 
													// may now have two underscores prepended so that they do not restrict the namespace 
													// of user programs. If the old names are required as in this example(without the 
													// underscores prepended), 
													// define the preprocessor macro __NOUNDERSCORES__ before including sysreg.h.
													// Only required with compiler patch 6.1.7 or later

#include "sysreg.h"
#include "signal.h"
#include "stdio.h"

#define N 64						// Number of words to transfer
int dm data_rx[N];					// Data received back from receiving processor memory
int dm data_tx[N] = {				// Data to be transmitted to external memory
#include "tx_data.dat"
};

							

section ("ext_data") int dm sdram_data[N];

struct TCB {
	int *DI;						// index
	int DX;							// count and stride in x direction
	int DY;							// count and stride in y direction
	int DP;							// DMA control word
};

section ("TCB_storage") struct TCB TCB_int_source, TCB_ext_dest, TCB_ext_source, TCB_int_dest, TCB_link_tx, TCB_link_rx;	// Structures for programming TCBs

__builtin_quad q;					// Temp quad for programming TCBs

void dma9_int();					// Only dma9 isr declared as all other interrupts have been disabled in setup of DP registers

void main(void)
{
	int i=0;	
	__builtin_sysreg_write(SYSCON,0x003879E7);		// 64-bit external bus for memory (MBUB)
	__builtin_sysreg_write(SDRCON,0x00005B05);		// SDRAM enabled, CAS LATENCY = three, Pipe Depth = 0, Page Boundry = 256,
													// Refresh Rate = 1200, PRC to RAS DELAY = 3, RAS TO PRC DELAY = 5,
													// INIT Sequence = REFRESH then MRS(MBUB)
	
	interrupt(SIGDMA9, dma9_int);					// Assign isr to DMA channel 9
													

/****************************** Define all members of Struct TCB ************************/	
	TCB_int_source.DI = data_tx;					// index points to source buffer
	TCB_int_source.DX = 4 | (N << 16);				// modify is 4 for quad-word transfers, count is N and must be shifted to upper half 
	TCB_int_source.DY = 0;							// only a 1 dimension DMA
	TCB_int_source.DP = (0x46450002);				// control word set for quad-word transfers to internal memory with interrupt enabled

	TCB_ext_dest.DI = sdram_data;					// index points to source buffer
	TCB_ext_dest.DX = 4 | (N << 16);				// modify is 4 for quad-word transfers, count is N and must be shifted to upper half 
	TCB_ext_dest.DY = 0;							// only a 1 dimension DMA
	TCB_ext_dest.DP = (0x86470003);					// control word set for quad-word transfers to internal memory with interrupt enabled

	TCB_ext_source.DI = sdram_data;					// index points to source buffer
	TCB_ext_source.DX = 4 | ((N/2) << 16);			// modify is 4 for quad-word transfers, count is N and must be shifted to upper half 
	TCB_ext_source.DY = 0;							// only a 1 dimension DMA
	TCB_ext_source.DP = (0x86530004);				// control word set for quad-word transfers to internal memory with interrupt enabled

	TCB_int_dest.DI = data_rx;						// index points to source buffer
	TCB_int_dest.DX = 4 | ((N/2) << 16);			// modify is 4 for quad-word transfers, count is N and must be shifted to upper half 
	TCB_int_dest.DY = 0;							// only a 1 dimension DMA
	TCB_int_dest.DP = (0x46400000);					// control word set for quad-word transfers to internal memory with interrupt enabled

	TCB_link_tx.DI = (sdram_data + (N/2));			// index points to source buffer
	TCB_link_tx.DX = 4 | ((N/2) << 16);				// modify is 4 for quad-word transfers, count is N and must be shifted to upper half 
	TCB_link_tx.DY = 0;								// only a 1 dimension DMA
	TCB_link_tx.DP = (0x86630005);					// control word set for quad-word transfers to internal memory with interrupt enabled

	TCB_link_rx.DI = (data_rx + (N/2));				// index points to source buffer
	TCB_link_rx.DX = 4 | ((N/2) << 16);				// modify is 4 for quad-word transfers, count is N and must be shifted to upper half 
	TCB_link_rx.DY = 0;								// only a 1 dimension DMA
	TCB_link_rx.DP = (0x47000000);					// control word set for quad-word transfers to internal memory with interrupt enabled


	__builtin_sysreg_write(LCTL1, 0x000004DA);		// Link port set up
	
	q = __builtin_compose_128((long long)TCB_int_source.DI | (long long)TCB_int_source.DX << 32, (long long)(TCB_int_source.DY | (long long)TCB_int_source.DP << 32));
	__builtin_sysreg_write4(DCS0, q);				// program the initial source TCB

	q = __builtin_compose_128((long long)TCB_ext_dest.DI | (long long)TCB_ext_dest.DX << 32, (long long)(TCB_ext_dest.DY | (long long)TCB_ext_dest.DP << 32));
	__builtin_sysreg_write4(DCD0, q);				// program the initial destination TCB


	while(1)										// Endless loop
		i=i-i;
}


/*********************************************************************************************************************************************/
/*	DMA9 Interrupt Service Routine ***********************************************************************************************************/
/*********************************************************************************************************************************************/
void dma9_int()										// ISR for DMA channel 9
{		

printf("\nAll DMA transfers completed\n"); 
	return;
}