external_mem.c

TS101 DMA演示程序,包括链路口DMA,二维DMA

/********************************************************************************************************************************/
/*		This program uses DMA channel 0 to DMA N words from internal memory to external SDRAM. Once this DMA has completed	    */
/*		DMA channel 0 is then set up to DMA the N words stored in external memory back to internal memory.					    */
/*																															    */
/*		The original data to be transmitted is stored in the file tx_data.dat. This data is placed in the buffer named "data_tx"*/
/*		within the internal memory.																								*/
/*																																*/
/*		The buffer in the external SDRAM where the data originally transmitted is stored into is named "sdram_data"				*/
/*																																*/
/*		The buffer named "data_rx" is where the data transmitted from SDRAM to internal memory is stored						*/
/********************************************************************************************************************************/
#define __NOUNDERSCORES__							// Depending on the compiler patch installed, the register names as defined in sysreg.h 
													// may now have two underscores prepended so that they do not restrict the namespace 
													// of user programs. If the old names are required as in this example(without the 
													// underscores prepended), 
													// define the preprocessor macro __NOUNDERSCORES__ before including sysreg.h.
													// Only required with compiler patch 6.1.7 or later

#include "sysreg.h"
#include "signal.h"
#include "stdio.h"

#define N 64										// Number of words to transfer

int dm data_tx[N] = {								// Data to be transmitted to external memory
#include "tx_data.dat"
};

int dm data_rx[N];									// Data received back from external memory

section ("SDRAM") int dm sdram_data[N];				// Data received in external memory

struct TCB {
	int *DI;										// index
	int DX;											// count and stride in x direction
	int DY;											// count and stride in y direction
	int DP;											// DMA control word
};

struct TCB TCB_temp;								// Temp structure for programming TCBs

__builtin_quad q;									// Temp quad for programming TCBs

void dma0_int();									// Prototype for interrupt service routine
void dma1_int();

void main(void)
{
	int i=0;	
	__builtin_sysreg_write(SYSCON,0x003879E7);		// 64-bit external bus for memory (MBUB)
	__builtin_sysreg_write(SDRCON,0x00005B05);		// SDRAM enabled, CAS LATENCY = three, Pipe Depth = 0, Page Boundry = 256,
													// Refresh Rate = 1200, PRC to RAS DELAY = 3, RAS TO PRC DELAY = 5,
													// INIT Sequence = REFRESH then MRS(MBUB)
	
	interrupt(SIGDMA0, dma0_int);					// Assign isr to DMA channel 0
													
	TCB_temp.DI = data_tx;							// index points to source buffer
	TCB_temp.DX = 4 | (N << 16);					// modify is 4 for quad-word transfers, count is N and must be shifted to upper half 
	TCB_temp.DY = 0;								// only a 1 dimension DMA
	TCB_temp.DP = 0x47000000;						// control word set for quad-word transfers to internal memory with interrupt enabled

	q = __builtin_compose_128((long long)TCB_temp.DI | (long long)TCB_temp.DX << 32, (long long)(TCB_temp.DY | (long long)TCB_temp.DP << 32));
	__builtin_sysreg_write4(DCS0, q);				// program the TCBs

	TCB_temp.DI = sdram_data;						// index points to buffer in SDRAM
	TCB_temp.DP = 0x87000000;						// control word set for quad-word transfers to external memory with interrupt enabled

	q = __builtin_compose_128((long long)TCB_temp.DI | (long long)TCB_temp.DX << 32, (long long)(TCB_temp.DY | (long long)TCB_temp.DP << 32));
	__builtin_sysreg_write4(DCD0, q);				// program the TCBs


	while(1)										// Endless loop
		i=i-i;
}


/*********************************************************************************************************************************************/
/*	DMA0 Interrupt Service Routine ***********************************************************************************************************/
/*********************************************************************************************************************************************/
void dma0_int()										// First isr for DMA channel 0
{		
	interrupt(SIGDMA1, dma1_int);					// Assign isr to DMA channel 1
	
	TCB_temp.DI = sdram_data;						// index points to source buffer in external memory
	TCB_temp.DP = 0x87000000;						// control word set for quad-word transfers to external memory with interrupt enabled

	q = __builtin_compose_128((long long)TCB_temp.DI | (long long)TCB_temp.DX << 32, (long long)(TCB_temp.DY | (long long)TCB_temp.DP << 32));
	__builtin_sysreg_write4(DCS1, q);				// program the TCBs

	TCB_temp.DI = data_rx;							// index points to destination buffer in internal memory
	TCB_temp.DP = 0x47000000;						// control word set for quad-word transfers to internal memory with interrupt enabled

	q = __builtin_compose_128((long long)TCB_temp.DI | (long long)TCB_temp.DX << 32, (long long)(TCB_temp.DY | (long long)TCB_temp.DP << 32));
	__builtin_sysreg_write4(DCD1, q);				// program the TCBs	
	
return;
}

/*********************************************************************************************************************************************/
/*	DMA1 Interrupt Service Routine ***********************************************************************************************************/
/*********************************************************************************************************************************************/
void dma1_int()										// First isr for DMA channel 1
{		
	printf("\nExternal memory DMAs completed\n"); 
	return;
}