taxt.map.eqn

FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。

C1L2 = CARRY(C1_q3[0]);


--S31L8 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~58
--operation mode is arithmetic

S31L8 = CARRY(!M2L63 & !M2L53 & !S31L6);


--M2L13 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[41]~13
--operation mode is normal

M2L13 = C1_stance[2] & (!S21L2);


--M2L23 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[41]~18
--operation mode is normal

M2L23 = S21L2 & (!C1_stance[2]);


--S31L01 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~63
--operation mode is arithmetic

S31L01 = CARRY(S31L11);


--S21L6 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~53
--operation mode is arithmetic

S21L6 = CARRY(!M2L03 & !M2L92 & !S21L01);


--S11L4 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~48
--operation mode is arithmetic

S11L4 = CARRY(!M2L42 & !M2L32 & !S11L8);


--M2L52 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[36]~23
--operation mode is normal

M2L52 = C1_stance[3] & (!S11L2);


--M2L62 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[36]~28
--operation mode is normal

M2L62 = S11L2 & (!C1_stance[3]);


--S21L8 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~58
--operation mode is arithmetic

S21L8 = CARRY(S21L11);


--F1_cx is ff_1_s:inst5|cx
--operation mode is normal

F1_cx_lut_out = !F1_a[1] & (F1_a[2] & F1_a[0]);
F1_cx = DFFEAS(F1_cx_lut_out, clk_zj, VCC, , , , , , );


--C1_stance[4] is speed:inst2|stance[4]
--operation mode is arithmetic

C1_stance[4]_lut_out = C1L73;
C1_stance[4] = DFFEAS(C1_stance[4]_lut_out, E1_clk_out, VCC, , , , , , );

--S01L1 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_6|add_sub_cella[1]~COUT
--operation mode is arithmetic

S01L1 = CARRY(C1_stance[4]);


--S3_add_sub_cella[1] is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_6|add_sub_cella[1]
--operation mode is arithmetic

S3_add_sub_cella[1] = C1_stance[4];

--S3L3 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_6|add_sub_cella[1]~COUT
--operation mode is arithmetic

S3L3 = CARRY(C1_stance[4]);


--M1L82 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[37]~883
--operation mode is normal

M1L82 = !S4L4 & (S3L4 & (!S3_add_sub_cella[1]) # !S3L4 & C1_stance[4]);


--S4L7 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~52
--operation mode is arithmetic

S4L7_carry_eqn = S4L21;
S4L7 = S4L7_carry_eqn $ (!M1L91 & !M1L02);

--S4L8 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~54
--operation mode is arithmetic

S4L8 = CARRY(!M1L91 & !M1L02 & !S4L21);


--M1L83 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[43]~884
--operation mode is normal

M1L83 = !S5L4 & (M1L82 # S4L4 & S4L7);


--S5L7 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~52
--operation mode is arithmetic

S5L7_carry_eqn = S5L01;
S5L7 = S5L7_carry_eqn $ (!M1L82 & !M1L72);

--S5L8 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~54
--operation mode is arithmetic

S5L8 = CARRY(!S5L01 & (M1L82 # M1L72));


--M1L73 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[43]~16
--operation mode is normal

M1L73 = S5L4 & S5L7;


--S6L5 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~56
--operation mode is arithmetic

S6L5 = CARRY(!S6L7 & (M1L63 # M1L53));


--C1_stance[5] is speed:inst2|stance[5]
--operation mode is arithmetic

C1_stance[5]_lut_out = C1L93;
C1_stance[5] = DFFEAS(C1_stance[5]_lut_out, E1_clk_out, VCC, , , , , , );

--S9L1 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_5|add_sub_cella[1]~COUT
--operation mode is arithmetic

S9L1 = CARRY(C1_stance[5]);


--S2L4 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~42
--operation mode is normal

S2L4_carry_eqn = S2L01;
S2L4 = !S2L4_carry_eqn;


--S2_add_sub_cella[1] is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_5|add_sub_cella[1]
--operation mode is arithmetic

S2_add_sub_cella[1] = C1_stance[5];

--S2L3 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_5|add_sub_cella[1]~COUT
--operation mode is arithmetic

S2L3 = CARRY(C1_stance[5]);


--M1L22 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[32]~885
--operation mode is normal

M1L22 = !S3L4 & (S2L4 & (!S2_add_sub_cella[1]) # !S2L4 & C1_stance[5]);


--S3L7 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~52
--operation mode is arithmetic

S3L7_carry_eqn = S3L21;
S3L7 = S3L7_carry_eqn $ (!M1L31 & !M1L41);

--S3L8 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~54
--operation mode is arithmetic

S3L8 = CARRY(!M1L31 & !M1L41 & !S3L21);


--M1L03 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[38]~886
--operation mode is normal

M1L03 = !S4L4 & (M1L22 # S3L4 & S3L7);


--S4L9 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~57
--operation mode is arithmetic

S4L9_carry_eqn = S4L8;
S4L9 = S4L9_carry_eqn $ (!M1L22 & !M1L12);

--S4L01 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~59
--operation mode is arithmetic

S4L01 = CARRY(!S4L8 & (M1L22 # M1L12));


--M1L92 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[38]~26
--operation mode is normal

M1L92 = S4L4 & S4L9;


--S61_add_sub_cella[1] is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_6|add_sub_cella[1]
--operation mode is arithmetic

S61_add_sub_cella[1] = S2L4;

--S61L3 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_6|add_sub_cella[1]~COUT
--operation mode is arithmetic

S61L3 = CARRY(S2L4);


--M3L01 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[37]~595
--operation mode is normal

M3L01 = !S71L4 & (S61L31 & (!S61_add_sub_cella[1]) # !S61L31 & S2L4);


--S71L7 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~51
--operation mode is arithmetic

S71L7_carry_eqn = S71L21;
S71L7 = S71L7_carry_eqn $ (!M3L1 & !M3L2);

--S71L8 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~53
--operation mode is arithmetic

S71L8 = CARRY(!M3L1 & !M3L2 & !S71L21);


--M3L81 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[43]~596
--operation mode is normal

M3L81 = !S81L4 & (M3L01 # S71L4 & S71L7);


--S81L11 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~61
--operation mode is arithmetic

S81L11_carry_eqn = S81L6;
S81L11 = S81L11_carry_eqn $ (!M3L01 & !M3L9);

--S81L21 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~63
--operation mode is arithmetic

S81L21 = CARRY(!S81L6 & (M3L01 # M3L9));


--M3L71 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[43]~16
--operation mode is normal

M3L71 = S81L4 & S81L11;


--S61L4 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~30
--operation mode is arithmetic

S61L4_carry_eqn = S61L7;
S61L4 = S1L4 $ (!S61L4_carry_eqn);

--S61L5 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~32
--operation mode is arithmetic

S61L5 = CARRY(!S1L4 & (!S61L7));


--S1L4 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~41
--operation mode is normal

S1L4_carry_eqn = S1L8;
S1L4 = !S1L4_carry_eqn;


--M3L21 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[38]~597
--operation mode is normal

M3L21 = !S71L4 & (S61L31 & S61L4 # !S61L31 & (S1L4));


--S71L9 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~56
--operation mode is arithmetic

S71L9_carry_eqn = S71L8;
S71L9 = S71L9_carry_eqn $ (!M3L3 & !M3L4);

--S71L01 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~58
--operation mode is arithmetic

S71L01 = CARRY(!S71L8 & (M3L3 # M3L4));


--M3L11 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[38]~26
--operation mode is normal

M3L11 = S71L4 & S71L9;


--C1_stance[6] is speed:inst2|stance[6]
--operation mode is arithmetic

C1_stance[6]_lut_out = C1L14;
C1_stance[6] = DFFEAS(C1_stance[6]_lut_out, E1_clk_out, VCC, , , , , , );

--S8L1 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]~COUT
--operation mode is arithmetic

S8L1 = CARRY(C1_stance[6]);


--S1_add_sub_cella[1] is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]
--operation mode is arithmetic

S1_add_sub_cella[1] = C1_stance[6];

--S1L3 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]~COUT
--operation mode is arithmetic

S1L3 = CARRY(C1_stance[6]);


--M1L61 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[27]~887
--operation mode is normal

M1L61 = !S2L4 & (S1L4 & (!S1_add_sub_cella[1]) # !S1L4 & C1_stance[6]);


--S2L5 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~47
--operation mode is arithmetic

S2L5_carry_eqn = S2L21;
S2L5 = S2L5_carry_eqn $ (!M1L7 & !M1L8);

--S2L6 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~49
--operation mode is arithmetic

S2L6 = CARRY(!M1L7 & !M1L8 & !S2L21);


--M1L42 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[33]~888
--operation mode is normal

M1L42 = !S3L4 & (M1L61 # S2L4 & S2L5);


--S3L9 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~57
--operation mode is arithmetic

S3L9_carry_eqn = S3L8;
S3L9 = S3L9_carry_eqn $ (!M1L61 & !M1L51);

--S3L01 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~59
--operation mode is arithmetic

S3L01 = CARRY(!S3L8 & (M1L61 # M1L51));


--M1L32 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[33]~36
--operation mode is normal

M1L32 = S3L4 & S3L9;


--R1L2 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_ne8:add_sub_3|add_sub_cella[2]~33
--operation mode is normal

R1L2_carry_eqn = R1L4;
R1L2 = R1L2_carry_eqn;


--C1_stance[7] is speed:inst2|stance[7]
--operation mode is arithmetic

C1_stance[7]_lut_out = C1L34;
C1_stance[7] = DFFEAS(C1_stance[7]_lut_out, E1_clk_out, VCC, , , , , , );

--R1L1 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_ne8:add_sub_3|a