taxt.map.eqn

FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。

--D1L04 is display:inst3|led7s6[5]~109
--operation mode is normal

D1L04 = !Y1L4 & (Z3L1 & (Z2L4 # !Z1L4) # !Z3L1 & Z2L4 & !Z1L4);


--D1L63 is display:inst3|led7s5[5]~132
--operation mode is normal

D1L63 = !M3L12 & (S6L1 & (M3L91 # !M3L02) # !S6L1 & M3L91 & !M3L02);


--D1L07 is display:inst3|led7s[5]~1747
--operation mode is normal

D1L07 = D1_flg1[0] & D1L04 # !D1_flg1[0] & (D1L63);


--D1L17 is display:inst3|led7s[5]~1748
--operation mode is normal

D1L17 = D1_flg1[2] & (D1L07 & !D1_flg1[1]) # !D1_flg1[2] & D1L96;


--D1L32 is display:inst3|led7s3[4]~135
--operation mode is normal

D1L32 = Z6L1 # Z4L4 & (!Z5L4);


--D1L61 is display:inst3|led7s2[4]~248
--operation mode is normal

D1L61 = S62L1 # M5L02 & (!M5L91);


--D1L26 is display:inst3|led7s[4]~1749
--operation mode is normal

D1L26 = D1_flg1[1] & (D1_flg1[0]) # !D1_flg1[1] & (D1_flg1[0] & D1L61 # !D1_flg1[0] & (D1L9));


--D1L36 is display:inst3|led7s[4]~1750
--operation mode is normal

D1L36 = D1_flg1[1] & (D1L26 & (D1L03) # !D1L26 & D1L32) # !D1_flg1[1] & (D1L26);


--D1L46 is display:inst3|led7s[4]~1751
--operation mode is normal

D1L46 = Z3L1 # Z1L4 & (!Z2L4);


--D1L56 is display:inst3|led7s[4]~1752
--operation mode is normal

D1L56 = M3L02 & (S91L4 & S91_add_sub_cella[1] # !S91L4 & (!S5L4));


--D1L66 is display:inst3|led7s[4]~1753
--operation mode is normal

D1L66 = D1_flg1[0] & D1L46 # !D1_flg1[0] & (S6L1 # D1L56);


--D1L76 is display:inst3|led7s[4]~1754
--operation mode is normal

D1L76 = D1_flg1[2] & (D1L66 & !D1_flg1[1]) # !D1_flg1[2] & D1L36;


--D1L22 is display:inst3|led7s3[3]~136
--operation mode is normal

D1L22 = !Y2L4 & (Z6L1 & (Z5L4 $ !Z4L4) # !Z6L1 & !Z5L4 & Z4L4);


--D1L51 is display:inst3|led7s2[3]~249
--operation mode is normal

D1L51 = !M5L12 & (S62L1 & (M5L91 $ !M5L02) # !S62L1 & !M5L91 & M5L02);


--D1L8 is display:inst3|led7s1[3]~254
--operation mode is normal

D1L8 = !M6L93 & (C1_money[0] & (M6L73 $ !M6L83) # !C1_money[0] & !M6L73 & M6L83);


--D1L85 is display:inst3|led7s[3]~1755
--operation mode is normal

D1L85 = D1_flg1[1] & (D1_flg1[0]) # !D1_flg1[1] & (D1_flg1[0] & D1L51 # !D1_flg1[0] & (D1L8));


--D1L92 is display:inst3|led7s4[3]~254
--operation mode is normal

D1L92 = !M2L93 & (C1_stance[0] & (M2L73 $ !M2L83) # !C1_stance[0] & !M2L73 & M2L83);


--D1L95 is display:inst3|led7s[3]~1756
--operation mode is normal

D1L95 = D1_flg1[1] & (D1L85 & (D1L92) # !D1L85 & D1L22) # !D1_flg1[1] & (D1L85);


--D1L93 is display:inst3|led7s6[3]~110
--operation mode is normal

D1L93 = !Y1L4 & (Z3L1 & (Z2L4 $ !Z1L4) # !Z3L1 & !Z2L4 & Z1L4);


--D1L53 is display:inst3|led7s5[3]~133
--operation mode is normal

D1L53 = !M3L12 & (S6L1 & (M3L91 $ !M3L02) # !S6L1 & !M3L91 & M3L02);


--D1L06 is display:inst3|led7s[3]~1757
--operation mode is normal

D1L06 = D1_flg1[0] & D1L93 # !D1_flg1[0] & (D1L53);


--D1L16 is display:inst3|led7s[3]~1758
--operation mode is normal

D1L16 = D1_flg1[2] & (D1L06 & !D1_flg1[1]) # !D1_flg1[2] & D1L95;


--D1L12 is display:inst3|led7s3[2]~137
--operation mode is normal

D1L12 = Z5L4 & (!Z6L1 & !Z4L4);


--D1L41 is display:inst3|led7s2[2]~250
--operation mode is normal

D1L41 = M5L91 & (!S62L1 & !M5L02);


--D1L25 is display:inst3|led7s[2]~1759
--operation mode is normal

D1L25 = D1_flg1[1] & (D1_flg1[0]) # !D1_flg1[1] & (D1_flg1[0] & D1L41 # !D1_flg1[0] & (D1L7));


--D1L35 is display:inst3|led7s[2]~1760
--operation mode is normal

D1L35 = D1_flg1[1] & (D1L25 & (D1L82) # !D1L25 & D1L12) # !D1_flg1[1] & (D1L25);


--D1L45 is display:inst3|led7s[2]~1761
--operation mode is normal

D1L45 = Z2L4 & D1_flg1[0] & !Z3L1 & !Z1L4;


--D1L55 is display:inst3|led7s[2]~1762
--operation mode is normal

D1L55 = !D1_flg1[0] & (S91L4 & (!S91_add_sub_cella[1]) # !S91L4 & S5L4);


--D1L65 is display:inst3|led7s[2]~1763
--operation mode is normal

D1L65 = D1L45 # D1L55 & !S6L1 & !M3L02;


--D1L75 is display:inst3|led7s[2]~1764
--operation mode is normal

D1L75 = D1_flg1[2] & (D1L65 & !D1_flg1[1]) # !D1_flg1[2] & D1L35;


--D1L02 is display:inst3|led7s3[1]~138
--operation mode is normal

D1L02 = Z4L4 & (Z6L1 $ Z5L4);


--D1L31 is display:inst3|led7s2[1]~251
--operation mode is normal

D1L31 = M5L02 & (S62L1 $ M5L91);


--D1L64 is display:inst3|led7s[1]~1765
--operation mode is normal

D1L64 = D1_flg1[1] & (D1_flg1[0]) # !D1_flg1[1] & (D1_flg1[0] & D1L31 # !D1_flg1[0] & (D1L6));


--D1L74 is display:inst3|led7s[1]~1766
--operation mode is normal

D1L74 = D1_flg1[1] & (D1L64 & (D1L72) # !D1L64 & D1L02) # !D1_flg1[1] & (D1L64);


--D1L84 is display:inst3|led7s[1]~1767
--operation mode is normal

D1L84 = D1L74 & (!D1_flg1[2]);


--D1L94 is display:inst3|led7s[1]~1768
--operation mode is normal

D1L94 = D1_flg1[0] & Z1L4 # !D1_flg1[0] & (M3L02);


--D1L43 is display:inst3|led7s5[1]~134
--operation mode is normal

D1L43 = S6L1 $ (S91L4 & !S91_add_sub_cella[1] # !S91L4 & (S5L4));


--D1L05 is display:inst3|led7s[1]~1769
--operation mode is normal

D1L05 = D1_flg1[0] & (Z3L1 $ Z2L4) # !D1_flg1[0] & D1L43;


--D1L15 is display:inst3|led7s[1]~1770
--operation mode is normal

D1L15 = D1L84 # D1L27 & D1L94 & D1L05;


--D1L91 is display:inst3|led7s3[0]~139
--operation mode is normal

D1L91 = !Z5L4 & !Y2L4 & (Z6L1 $ Z4L4);


--D1L21 is display:inst3|led7s2[0]~252
--operation mode is normal

D1L21 = !M5L91 & !M5L12 & (S62L1 $ M5L02);


--D1L5 is display:inst3|led7s1[0]~255
--operation mode is normal

D1L5 = !M6L73 & !M6L93 & (C1_money[0] $ M6L83);


--D1L24 is display:inst3|led7s[0]~1771
--operation mode is normal

D1L24 = D1_flg1[1] & (D1_flg1[0]) # !D1_flg1[1] & (D1_flg1[0] & D1L21 # !D1_flg1[0] & (D1L5));


--D1L62 is display:inst3|led7s4[0]~255
--operation mode is normal

D1L62 = !M2L73 & !M2L93 & (C1_stance[0] $ M2L83);


--D1L34 is display:inst3|led7s[0]~1772
--operation mode is normal

D1L34 = D1_flg1[1] & (D1L24 & (D1L62) # !D1L24 & D1L91) # !D1_flg1[1] & (D1L24);


--D1L83 is display:inst3|led7s6[0]~111
--operation mode is normal

D1L83 = !Z2L4 & !Y1L4 & (Z3L1 $ Z1L4);


--D1L33 is display:inst3|led7s5[0]~135
--operation mode is normal

D1L33 = !M3L91 & !M3L12 & (S6L1 $ M3L02);


--D1L44 is display:inst3|led7s[0]~1773
--operation mode is normal

D1L44 = D1_flg1[0] & D1L83 # !D1_flg1[0] & (D1L33);


--D1L54 is display:inst3|led7s[0]~1774
--operation mode is normal

D1L54 = D1_flg1[2] & (D1L44 & !D1_flg1[1]) # !D1_flg1[2] & D1L34;


--D1L28 is display:inst3|site[5]~76
--operation mode is normal

D1L28 = D1_flg1[2] & D1_flg1[0];


--D1L18 is display:inst3|site[4]~77
--operation mode is normal

D1L18 = D1_flg1[2] & (!D1_flg1[0]);


--D1L08 is display:inst3|site[3]~78
--operation mode is normal

D1L08 = D1_flg1[1] & D1_flg1[0];


--D1L97 is display:inst3|site[2]~79
--operation mode is normal

D1L97 = D1_flg1[1] & (!D1_flg1[0]);


--D1L87 is display:inst3|site[1]~80
--operation mode is normal

D1L87 = D1_flg1[0] & (!D1_flg1[2] & !D1_flg1[1]);


--D1L77 is display:inst3|site[0]~81
--operation mode is normal

D1L77 = !D1_flg1[2] & !D1_flg1[1] & !D1_flg1[0];


--F1_clk_out is ff_1_s:inst5|clk_out
--operation mode is normal

F1_clk_out_lut_out = !F1_clk_out;
F1_clk_out = DFFEAS(F1_clk_out_lut_out, F1_cx, VCC, , , , , , );


--S6L3 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~51
--operation mode is arithmetic

S6L3 = CARRY(!M1L83 & !M1L73 & !S6L5);


--S5L6 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~49
--operation mode is arithmetic

S5L6 = CARRY(!M1L03 & !M1L92 & !S5L8);


--S91L01 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~58
--operation mode is arithmetic

S91L01 = CARRY(!M3L81 & !M3L71 & !S91L8);


--S91L21 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~63
--operation mode is arithmetic

S91L21 = CARRY(S91L31);


--S81L8 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~53
--operation mode is arithmetic

S81L8 = CARRY(!M3L21 & !M3L11 & !S81L21);


--S4L6 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~49
--operation mode is arithmetic

S4L6 = CARRY(!M1L42 & !M1L32 & !S4L01);


--S3L6 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~49
--operation mode is arithmetic

S3L6 = CARRY(!M1L81 & !M1L71 & !S3L01);


--S71L6 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~48
--operation mode is arithmetic

S71L6 = CARRY(!M3L5 & !M3L6 & !S71L01);