taxt.map.eqn

FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。

--S32L4 is d_to_b:inst1|lpm_divide:div_rtl_1|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~42
--operation mode is normal

S32L4_carry_eqn = S32L6;
S32L4 = !S32L4_carry_eqn;


--S03L4 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~41
--operation mode is normal

S03L4_carry_eqn = S03L6;
S03L4 = !S03L4_carry_eqn;


--S03_add_sub_cella[1] is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[1]
--operation mode is arithmetic

S03_add_sub_cella[1] = S32L4;

--S03L3 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[1]~COUT
--operation mode is arithmetic

S03L3 = CARRY(S32L4);


--M5L61 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[42]~593
--operation mode is normal

M5L61 = !S13L4 & (S03L4 & (!S03_add_sub_cella[1]) # !S03L4 & S32L4);


--S13L5 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~46
--operation mode is arithmetic

S13L5_carry_eqn = S13L01;
S13L5 = S13L5_carry_eqn $ (!M5L7 & !M5L8);

--S13L6 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~48
--operation mode is arithmetic

S13L6 = CARRY(!M5L7 & !M5L8 & !S13L01);


--M5L51 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[42]~17
--operation mode is normal

M5L51 = S13L4 & S13L5;


--M5L12 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[48]~594
--operation mode is normal

M5L12 = S23L4 & S23L7 # !S23L4 & (M5L61 # M5L51);


--D1L81 is display:inst3|led7s2[6]~246
--operation mode is normal

D1L81 = M5L12 # M5L91 & (!M5L02 # !S62L1) # !M5L91 & (M5L02);


--C1_money[0] is speed:inst2|money[0]
--operation mode is normal

C1_money[0]_lut_out = C1_time[0] # !C1L941;
C1_money[0] = DFFEAS(C1_money[0]_lut_out, E1_clk_out, VCC, , , , , , );


--S83L4 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~41
--operation mode is normal

S83L4_carry_eqn = S83L01;
S83L4 = !S83L4_carry_eqn;


--S83_add_sub_cella[1] is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]
--operation mode is arithmetic

S83_add_sub_cella[1] = C1_money[1];

--S83L3 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUT
--operation mode is arithmetic

S83L3 = CARRY(S83_add_sub_cella[1]);


--M6L73 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[46]~1041
--operation mode is normal

M6L73 = S83L4 $ S83_add_sub_cella[1];


--S83L5 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~46
--operation mode is arithmetic

S83L5_carry_eqn = S83L21;
S83L5 = S83L5_carry_eqn $ (!M6L13 & !M6L23);

--S83L6 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~48
--operation mode is arithmetic

S83L6 = CARRY(!M6L13 & !M6L23 & !S83L21);


--S73L4 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~41
--operation mode is normal

S73L4_carry_eqn = S73L8;
S73L4 = !S73L4_carry_eqn;


--S73_add_sub_cella[1] is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[1]
--operation mode is arithmetic

S73_add_sub_cella[1] = C1_money[2];

--S73L3 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[1]~COUT
--operation mode is arithmetic

S73L3 = CARRY(S73_add_sub_cella[1]);


--M6L83 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[47]~1042
--operation mode is normal

M6L83 = S83L4 & S83L5 # !S83L4 & (S73L4 $ S73_add_sub_cella[1]);


--S83L7 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~51
--operation mode is arithmetic

S83L7_carry_eqn = S83L6;
S83L7 = S83L7_carry_eqn $ (!M6L43 & !M6L33);

--S83L8 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~53
--operation mode is arithmetic

S83L8 = CARRY(!S83L6 & (M6L43 # M6L33));


--S63L4 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~41
--operation mode is normal

S63L4_carry_eqn = S63L6;
S63L4 = !S63L4_carry_eqn;


--S63_add_sub_cella[1] is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[1]
--operation mode is arithmetic

S63_add_sub_cella[1] = C1_money[3];

--S63L3 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[1]~COUT
--operation mode is arithmetic

S63L3 = CARRY(S63_add_sub_cella[1]);


--M6L43 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[42]~1043
--operation mode is normal

M6L43 = !S73L4 & (S63L4 $ S63_add_sub_cella[1]);


--S73L5 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~46
--operation mode is arithmetic

S73L5_carry_eqn = S73L01;
S73L5 = S73L5_carry_eqn $ (!M6L52 & !M6L62);

--S73L6 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~48
--operation mode is arithmetic

S73L6 = CARRY(!M6L52 & !M6L62 & !S73L01);


--M6L33 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[42]~17
--operation mode is normal

M6L33 = S73L4 & S73L5;


--M6L93 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[48]~1044
--operation mode is normal

M6L93 = S83L4 & S83L7 # !S83L4 & (M6L43 # M6L33);


--D1L11 is display:inst3|led7s1[6]~252
--operation mode is normal

D1L11 = M6L93 # M6L73 & (!M6L83 # !C1_money[0]) # !M6L73 & (M6L83);


--D1L47 is display:inst3|led7s[6]~1742
--operation mode is normal

D1L47 = D1_flg1[1] & (D1_flg1[0]) # !D1_flg1[1] & (D1_flg1[0] & !D1L81 # !D1_flg1[0] & (!D1L11));


--C1_stance[0] is speed:inst2|stance[0]
--operation mode is normal

C1_stance[0]_lut_out = C1L1;
C1_stance[0] = DFFEAS(C1_stance[0]_lut_out, E1_clk_out, VCC, , , , , , );


--S31L2 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~41
--operation mode is normal

S31L2_carry_eqn = S31L8;
S31L2 = !S31L2_carry_eqn;


--C1_stance[1] is speed:inst2|stance[1]
--operation mode is arithmetic

C1_stance[1]_lut_out = C1L3;
C1_stance[1] = DFFEAS(C1_stance[1]_lut_out, E1_clk_out, VCC, , , , , , );

--S31L1 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUT
--operation mode is arithmetic

S31L1 = CARRY(C1_stance[1]);


--M2L73 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[46]~1041
--operation mode is normal

M2L73 = S31L2 $ C1_stance[1];


--S31L3 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~46
--operation mode is arithmetic

S31L3_carry_eqn = S31L01;
S31L3 = S31L3_carry_eqn $ (!M2L13 & !M2L23);

--S31L4 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~48
--operation mode is arithmetic

S31L4 = CARRY(!M2L13 & !M2L23 & !S31L01);


--S21L2 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~41
--operation mode is normal

S21L2_carry_eqn = S21L6;
S21L2 = !S21L2_carry_eqn;


--C1_stance[2] is speed:inst2|stance[2]
--operation mode is arithmetic

C1_stance[2]_lut_out = C1L5;
C1_stance[2] = DFFEAS(C1_stance[2]_lut_out, E1_clk_out, VCC, , , , , , );

--S21L1 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[1]~COUT
--operation mode is arithmetic

S21L1 = CARRY(C1_stance[2]);


--M2L83 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[47]~1042
--operation mode is normal

M2L83 = S31L2 & S31L3 # !S31L2 & (S21L2 $ C1_stance[2]);


--S31L5 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~51
--operation mode is arithmetic

S31L5_carry_eqn = S31L4;
S31L5 = S31L5_carry_eqn $ (!M2L43 & !M2L33);

--S31L6 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~53
--operation mode is arithmetic

S31L6 = CARRY(!S31L4 & (M2L43 # M2L33));


--S11L2 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~41
--operation mode is normal

S11L2_carry_eqn = S11L4;
S11L2 = !S11L2_carry_eqn;


--C1_stance[3] is speed:inst2|stance[3]
--operation mode is arithmetic

C1_stance[3]_lut_out = C1L7;
C1_stance[3] = DFFEAS(C1_stance[3]_lut_out, E1_clk_out, VCC, , , , , , );

--S11L1 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[1]~COUT
--operation mode is arithmetic

S11L1 = CARRY(C1_stance[3]);


--M2L43 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[42]~1043
--operation mode is normal

M2L43 = !S21L2 & (S11L2 $ C1_stance[3]);


--S21L3 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~46
--operation mode is arithmetic

S21L3_carry_eqn = S21L8;
S21L3 = S21L3_carry_eqn $ (!M2L52 & !M2L62);

--S21L4 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~48
--operation mode is arithmetic

S21L4 = CARRY(!M2L52 & !M2L62 & !S21L8);


--M2L33 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[42]~17
--operation mode is normal

M2L33 = S21L2 & S21L3;


--M2L93 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[48]~1044
--operation mode is normal

M2L93 = S31L2 & S31L5 # !S31L2 & (M2L43 # M2L33);


--D1L23 is display:inst3|led7s4[6]~252
--operation mode is normal

D1L23 = M2L93 # M2L73 & (!M2L83 # !C1_stance[0]) # !M2L73 & (M2L83);


--D1L57 is display:inst3|led7s[6]~1743
--operation mode is normal

D1L57 = D1_flg1[1] & (D1L47 & (!D1L23) # !D1L47 & !D1L52) # !D1_flg1[1] & (D1L47);


--D1L67 is display:inst3|led7s[6]~1744
--operation mode is normal

D1L67 = D1L37 # D1L57 & (!D1_flg1[2]);


--D1L42 is display:inst3|led7s3[5]~134
--operation mode is normal

D1L42 = !Y2L4 & (Z6L1 & (Z5L4 # !Z4L4) # !Z6L1 & Z5L4 & !Z4L4);


--D1L71 is display:inst3|led7s2[5]~247
--operation mode is normal

D1L71 = !M5L12 & (S62L1 & (M5L91 # !M5L02) # !S62L1 & M5L91 & !M5L02);


--D1L01 is display:inst3|led7s1[5]~253
--operation mode is normal

D1L01 = !M6L93 & (C1_money[0] & (M6L73 # !M6L83) # !C1_money[0] & M6L73 & !M6L83);


--D1L86 is display:inst3|led7s[5]~1745
--operation mode is normal

D1L86 = D1_flg1[1] & (D1_flg1[0]) # !D1_flg1[1] & (D1_flg1[0] & D1L71 # !D1_flg1[0] & (D1L01));


--D1L13 is display:inst3|led7s4[5]~253
--operation mode is normal

D1L13 = !M2L93 & (C1_stance[0] & (M2L73 # !M2L83) # !C1_stance[0] & M2L73 & !M2L83);


--D1L96 is display:inst3|led7s[5]~1746
--operation mode is normal

D1L96 = D1_flg1[1] & (D1L86 & (D1L13) # !D1L86 & D1L42) # !D1_flg1[1] & (D1L86);