taxt.v

来自「FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。」· Verilog 代码 · 共 70 行

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.

module taxt(
	start,
	push,
	clk_sp,
	clk_zj,
	led7s,
	site
);

input	start;
input	push;
input	clk_sp;
input	clk_zj;
output	[6:0] led7s;
output	[5:0] site;

wire	[9:0] SYNTHESIZED_WIRE_0;
wire	[9:0] SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;
wire	SYNTHESIZED_WIRE_3;
wire	SYNTHESIZED_WIRE_12;
wire	[3:0] SYNTHESIZED_WIRE_5;
wire	[3:0] SYNTHESIZED_WIRE_6;
wire	[3:0] SYNTHESIZED_WIRE_7;
wire	[3:0] SYNTHESIZED_WIRE_8;
wire	[3:0] SYNTHESIZED_WIRE_9;
wire	[3:0] SYNTHESIZED_WIRE_10;





d_to_b	b2v_inst(.ax(SYNTHESIZED_WIRE_0),
.q1(SYNTHESIZED_WIRE_8),.q2(SYNTHESIZED_WIRE_9),.q3(SYNTHESIZED_WIRE_10));

d_to_b	b2v_inst1(.ax(SYNTHESIZED_WIRE_1),
.q1(SYNTHESIZED_WIRE_5),.q2(SYNTHESIZED_WIRE_6),.q3(SYNTHESIZED_WIRE_7));

speed	b2v_inst2(.start(start),
.push(push),.clk_1s(SYNTHESIZED_WIRE_2),.clk_sp(SYNTHESIZED_WIRE_3),.money(SYNTHESIZED_WIRE_1),.stance(SYNTHESIZED_WIRE_0));

display	b2v_inst3(.clk_d(SYNTHESIZED_WIRE_12),
.q1(SYNTHESIZED_WIRE_5),.q2(SYNTHESIZED_WIRE_6),.q3(SYNTHESIZED_WIRE_7),.q4(SYNTHESIZED_WIRE_8),.q5(SYNTHESIZED_WIRE_9),.q6(SYNTHESIZED_WIRE_10),.led7s(led7s),.site(site));

frq	b2v_inst4(.clk_in(SYNTHESIZED_WIRE_12),
.clk_out(SYNTHESIZED_WIRE_2));

ff_1_s	b2v_inst5(.clk_in(clk_zj),
.clk_out(SYNTHESIZED_WIRE_12));

ff_100_s	b2v_inst6(.clk_in(clk_sp),
.clk_out(SYNTHESIZED_WIRE_3));


endmodule