display.vhd

FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity display is  --display entity
port(clk_d:in std_logic;  --scanning frequency of display 
     q6:in integer range 9 downto 0;
     q5:in integer range 9 downto 0;
     q4:in integer range 9 downto 0;
     q3:in integer range 9 downto 0;
     q2:in integer range 9 downto 0;
     q1:in integer range 9 downto 0;  --input data (money and stance)
     site:out std_logic_vector (5 downto 0);  --words site selecte
     led7s:out std_logic_vector (6 downto 0)); --words form display
end;

architecture a of display is
signal flg1:integer range 5 downto 0;  --words site flag 
signal led7s6,led7s5,led7s4,led7s3,led7s2,led7s1:std_logic_vector (6 downto 0);

begin

process(clk_d)   --process1
begin
if clk_d'event and clk_d='1' then
   if flg1=5 then
      flg1<=0;
   else  flg1<=flg1+1;
   end if;
end if;
end process;


process(q6)   --字形显示译码
begin
case q6 is

when 0 => led7s6<="1000000";
when 1 => led7s6<="1111001";
when 2 => led7s6<="0100100";
when 3 => led7s6<="0110000";
when 4 => led7s6<="0011001";
when 5 => led7s6<="0010010";
when 6 => led7s6<="0000010";
when 7 => led7s6<="1111000";
when 8 => led7s6<="0000000";
when 9 => led7s6<="0010000";
when others =>null;
end case;
end process;

process(q5) 
begin
case q5 is

when 0 => led7s5<="1000000";
when 1 => led7s5<="1111001";
when 2 => led7s5<="0100100";
when 3 => led7s5<="0110000";
when 4 => led7s5<="0011001";
when 5 => led7s5<="0010010";
when 6 => led7s5<="0000010";
when 7 => led7s5<="1111000";
when 8 => led7s5<="0000000";
when 9 => led7s5<="0010000";
when others =>null;
end case;
end process;

process(q4) 
begin
case q4 is

when 0 => led7s4<="1000000";
when 1 => led7s4<="1111001";
when 2 => led7s4<="0100100";
when 3 => led7s4<="0110000";
when 4 => led7s4<="0011001";
when 5 => led7s4<="0010010";
when 6 => led7s4<="0000010";
when 7 => led7s4<="1111000";
when 8 => led7s4<="0000000";
when 9 => led7s4<="0010000";
when others =>null;
end case;
end process;

process(q3) 
begin
case q3 is

when 0 => led7s3<="1000000";
when 1 => led7s3<="1111001";
when 2 => led7s3<="0100100";
when 3 => led7s3<="0110000";
when 4 => led7s3<="0011001";
when 5 => led7s3<="0010010";
when 6 => led7s3<="0000010";
when 7 => led7s3<="1111000";
when 8 => led7s3<="0000000";
when 9 => led7s3<="0010000";
when others =>null;
end case;
end process;

process(q2) 
begin
case q2 is

when 0 => led7s2<="1000000";
when 1 => led7s2<="1111001";
when 2 => led7s2<="0100100";
when 3 => led7s2<="0110000";
when 4 => led7s2<="0011001";
when 5 => led7s2<="0010010";
when 6 => led7s2<="0000010";
when 7 => led7s2<="1111000";
when 8 => led7s2<="0000000";
when 9 => led7s2<="0010000";
when others =>null;
end case;
end process;

process(q1) 
begin
case q1 is

when 0 => led7s1<="1000000";
when 1 => led7s1<="1111001";
when 2 => led7s1<="0100100";
when 3 => led7s1<="0110000";
when 4 => led7s1<="0011001";
when 5 => led7s1<="0010010";
when 6 => led7s1<="0000010";
when 7 => led7s1<="1111000";
when 8 => led7s1<="0000000";
when 9 => led7s1<="0010000";
when others =>null;
end case;
end process;


process(flg1,led7s6,led7s5,led7s4,led7s3,led7s2,led7s1)
begin
case flg1 is
when 5 => site<="100000" ;led7s<=led7s6;
when 4 => site<="010000" ;led7s<=led7s5;
when 3 => site<="001000" ;led7s<=led7s4;
when 2 => site<="000100" ;led7s<=led7s3;
when 1 => site<="000010" ;led7s<=led7s2;
when 0 => site<="000001" ;led7s<=led7s1;
when others => null;
end case;
end process;

end;