taxt.tan.summary

FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.418 ns
From           : push
To             : speed:inst2|kilo
From Clock     : 
To Clock       : clk_sp
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 61.465 ns
From           : speed:inst2|money[7]
To             : led7s[6]
From Clock     : clk_zj
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 11.203 ns
From           : start
To             : speed:inst2|mint
From Clock     : 
To Clock       : clk_zj
Failed Paths   : 0

Type           : Clock Setup: 'clk_zj'
Slack          : N/A
Required Time  : None
Actual Time    : 79.88 MHz ( period = 12.519 ns )
From           : speed:inst2|time[2]
To             : speed:inst2|money[8]
From Clock     : clk_zj
To Clock       : clk_zj
Failed Paths   : 0

Type           : Clock Setup: 'clk_sp'
Slack          : N/A
Required Time  : None
Actual Time    : 232.29 MHz ( period = 4.305 ns )
From           : speed:inst2|q3[2]
To             : speed:inst2|q3[5]
From Clock     : clk_sp
To Clock       : clk_sp
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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