ff_100_s.vhd

FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。

library ieee;
use ieee.std_logic_1164.all;
entity ff_100_s is                   --50Mhz分成50hz  fl2
port(clk_in:in bit;
     
     clk_out:buffer  bit);
end;
architecture a of ff_100_s is
signal cx: bit;
begin 
process(clk_in)
variable a:integer range 2 downto 0;
begin
if clk_in'event and clk_in='1' then
   if a=2 then cx<='1';a:=0;
   else a:=a+1;cx<='0';
   end if;
end if;
end process;

process(cx)
begin
if cx'event and cx='1' then
clk_out<=not clk_out;
end if;
end process;
end;