frq.vhd

FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。

library ieee;
use ieee.std_logic_1164.all;
entity frq is                   --50Mhz分
port(clk_in:in bit;
     
     clk_out:buffer  bit);
end;
architecture a of frq is
signal clk2: bit;
begin 
process(clk_in)
variable a:integer range 3 downto 1;
begin
if clk_in'event and clk_in='1' then
   if a=3 then clk2<='1';a:=1;
   else a:=a+1;clk2<='0';
   end if;
end if;
end process;

process(clk2)
begin
if clk2'event and clk2='1' then
clk_out<=not clk_out;
end if;
end process;
end;