taxt.fit.qmsg

FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 11 00:35:31 2008 " "Info: Processing started: Thu Dec 11 00:35:31 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off taxt -c taxt " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off taxt -c taxt" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "taxt EP1C20F324C8 " "Info: Selected device EP1C20F324C8 for design \"taxt\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C4F324C8 " "Info: Device EP1C4F324C8 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12F324C8 " "Info: Device EP1C12F324C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "17 17 " "Info: No exact pin location assignment(s) for 17 pins of 17 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "led7s\[6\] " "Info: Pin led7s\[6\] not assigned to an exact location on the device" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 176 736 912 192 "led7s\[6..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "led7s\[6\]" } } } } { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "" { led7s[6] } "NODE_NAME" } "" } } { "E:/study/eda/TAXT/taxt.fld" "" { Floorplan "E:/study/eda/TAXT/taxt.fld" "" "" { led7s[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "led7s\[5\] " "Info: Pin led7s\[5\] not assigned to an exact location on the device" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 176 736 912 192 "led7s\[6..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "led7s\[5\]" } } } } { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "" { led7s[5] } "NODE_NAME" } "" } } { "E:/study/eda/TAXT/taxt.fld" "" { Floorplan "E:/study/eda/TAXT/taxt.fld" "" "" { led7s[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "led7s\[4\] " "Info: Pin led7s\[4\] not assigned to an exact location on the device" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 176 736 912 192 "led7s\[6..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "led7s\[4\]" } } } } { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "" { led7s[4] } "NODE_NAME" } "" } } { "E:/study/eda/TAXT/taxt.fld" "" { Floorplan "E:/study/eda/TAXT/taxt.fld" "" "" { led7s[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "led7s\[3\] " "Info: Pin led7s\[3\] not assigned to an exact location on the device" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 176 736 912 192 "led7s\[6..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "led7s\[3\]" } } } } { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "" { led7s[3] } "NODE_NAME" } "" } } { "E:/study/eda/TAXT/taxt.fld" "" { Floorplan "E:/study/eda/TAXT/taxt.fld" "" "" { led7s[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "led7s\[2\] " "Info: Pin led7s\[2\] not assigned to an exact location on the device" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 176 736 912 192 "led7s\[6..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "led7s\[2\]" } } } } { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "" { led7s[2] } "NODE_NAME" } "" } } { "E:/study/eda/TAXT/taxt.fld" "" { Floorplan "E:/study/eda/TAXT/taxt.fld" "" "" { led7s[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "led7s\[1\] " "Info: Pin led7s\[1\] not assigned to an exact location on the device" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 176 736 912 192 "led7s\[6..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "led7s\[1\]" } } } } { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "" { led7s[1] } "NODE_NAME" } "" } } { "E:/study/eda/TAXT/taxt.fld" "" { Floorplan "E:/study/eda/TAXT/taxt.fld" "" "" { led7s[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "led7s\[0\] " "Info: Pin led7s\[0\] not assigned to an exact location on the device" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 176 736 912 192 "led7s\[6..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "led7s\[0\]" } } } } { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "" { led7s[0] } "NODE_NAME" } "" } } { "E:/study/eda/TAXT/taxt.fld" "" { Floorplan "E:/study/eda/TAXT/taxt.fld" "" "" { led7s[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "site\[5\] " "Info: Pin site\[5\] not assigned to an exact location on the device" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 136 736 912 152 "site\[5..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "site\[5\]" } } } } { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "" { site[5] } "NODE_NAME" } "" } } { "E:/study/eda/TAXT/taxt.fld" "" { Floorplan "E:/study/eda/TAXT/taxt.fld" "" "" { site[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "site\[4\] " "Info: Pin site\[4\] not assigned to an exact location on the device" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 136 736 912 152 "site\[5..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "site\[4\]" } } } } { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "" { site[4] } "NODE_NAME" } "" } } { "E:/study/eda/TAXT/taxt.fld" "" { Floorplan "E:/study/eda/TAXT/taxt.fld" "" "" { site[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "site\[3\] " "Info: Pin site\[3\] not assigned to an exact location on the device" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 136 736 912 152 "site\[5..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "site\[3\]" } } } } { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "" { site[3] } "NODE_NAME" } "" } } { "E:/study/eda/TAXT/taxt.fld" "" { Floorplan "E:/study/eda/TAXT/taxt.fld" "" "" { site[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "site\[2\] " "Info: Pin site\[2\] not assigned to an exact location on the device" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 136 736 912 152 "site\[5..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "site\[2\]" } } } } { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "" { site[2] } "NODE_NAME" } "" } } { "E:/study/eda/TAXT/taxt.fld" "" { Floorplan "E:/study/eda/TAXT/taxt.fld" "" "" { site[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "site\[1\] " "Info: Pin site\[1\] not assigned to an exact location on the device" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 136 736 912 152 "site\[5..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "site\[1\]" } } } } { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "" { site[1] } "NODE_NAME" } "" } } { "E:/study/eda/TAXT/taxt.fld" "" { Floorplan "E:/study/eda/TAXT/taxt.fld" "" "" { site[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "site\[0\] " "Info: Pin site\[0\] not assigned to an exact location on the device" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 136 736 912 152 "site\[5..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "site\[0\]" } } } } { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "" { site[0] } "NODE_NAME" } "" } } { "E:/study/eda/TAXT/taxt.fld" "" { Floorplan "E:/study/eda/TAXT/taxt.fld" "" "" { site[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "push " "Info: Pin push not assigned to an exact location on the device" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 296 96 264 312 "push" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "push" } } } } { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "" { push } "NODE_NAME" } "" } } { "E:/study/eda/TAXT/taxt.fld" "" { Floorplan "E:/study/eda/TAXT/taxt.fld" "" "" { push } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "start " "Info: Pin start not assigned to an exact location on the device" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 280 96 264 296 "start" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "start" } } } } { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "" { start } "NODE_NAME" } "" } } { "E:/study/eda/TAXT/taxt.fld" "" { Floorplan "E:/study/eda/TAXT/taxt.fld" "" "" { start } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clk_zj " "Info: Pin clk_zj not assigned to an exact location on the device" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 96 48 216 112 "clk_zj" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_zj" } } } } { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "" { clk_zj } "NODE_NAME" } "" } } { "E:/study/eda/TAXT/taxt.fld" "" { Floorplan "E:/study/eda/TAXT/taxt.fld" "" "" { clk_zj } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clk_sp " "Info: Pin clk_sp not assigned to an exact location on the device" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 344 0 168 360 "clk_sp" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_sp" } } } } { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "" { clk_sp } "NODE_NAME" } "" } } { "E:/study/eda/TAXT/taxt.fld" "" { Floorplan "E:/study/eda/TAXT/taxt.fld" "" "" { clk_sp } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk_zj Global clock in PIN J4 " "Info: Automatically promoted signal \"clk_zj\" to use Global clock in PIN J4" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 96 48 216 112 "clk_zj" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk_sp Global clock in PIN J3 " "Info: Automatically promoted signal \"clk_sp\" to use Global clock in PIN J3" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 344 0 168 360 "clk_sp" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "frq:inst4\|clk_out Global clock " "Info: Automatically promoted some destinations of signal \"frq:inst4\|clk_out\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "frq:inst4\|clk_out " "Info: Destination \"frq:inst4\|clk_out\" may be non-global or may not use global clock" {  } { { "frq.vhd" "" { Text "E:/study/eda/TAXT/frq.vhd" 6 -1 0 } }  } 0}  } { { "frq.vhd" "" { Text "E:/study/eda/TAXT/frq.vhd" 6 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "ff_100_s:inst6\|clk_out Global clock " "Info: Automatically promoted some destinations of signal \"ff_100_s:inst6\|clk_out\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ff_100_s:inst6\|clk_out " "Info: Destination \"ff_100_s:inst6\|clk_out\" may be non-global or may not use global clock" {  } { { "ff_100_s.vhd" "" { Text "E:/study/eda/TAXT/ff_100_s.vhd" 6 -1 0 } }  } 0}  } { { "ff_100_s.vhd" "" { Text "E:/study/eda/TAXT/ff_100_s.vhd" 6 -1 0 } }  } 0}