taxt.map.qmsg

FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 11 00:34:55 2008 " "Info: Processing started: Thu Dec 11 00:34:55 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off taxt -c taxt " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off taxt -c taxt" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d_to_b.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file d_to_b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 d_to_b-one " "Info: Found design unit 1: d_to_b-one" {  } { { "d_to_b.vhd" "" { Text "E:/study/eda/TAXT/d_to_b.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 d_to_b " "Info: Found entity 1: d_to_b" {  } { { "d_to_b.vhd" "" { Text "E:/study/eda/TAXT/d_to_b.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "display.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file display.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 display-a " "Info: Found design unit 1: display-a" {  } { { "display.vhd" "" { Text "E:/study/eda/TAXT/display.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 display " "Info: Found entity 1: display" {  } { { "display.vhd" "" { Text "E:/study/eda/TAXT/display.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "frq.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file frq.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 frq-a " "Info: Found design unit 1: frq-a" {  } { { "frq.vhd" "" { Text "E:/study/eda/TAXT/frq.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 frq " "Info: Found entity 1: frq" {  } { { "frq.vhd" "" { Text "E:/study/eda/TAXT/frq.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "speed.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file speed.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 speed-a " "Info: Found design unit 1: speed-a" {  } { { "speed.vhd" "" { Text "E:/study/eda/TAXT/speed.vhd" 15 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 speed " "Info: Found entity 1: speed" {  } { { "speed.vhd" "" { Text "E:/study/eda/TAXT/speed.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "taxt.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file taxt.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 taxt " "Info: Found entity 1: taxt" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "taxt " "Info: Elaborating entity \"taxt\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "display display:inst3 " "Info: Elaborating entity \"display\" for hierarchy \"display:inst3\"" {  } { { "taxt.bdf" "inst3" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 240 664 808 400 "inst3" "" } } } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "display.vhd(47) " "Info: VHDL Case Statement information at display.vhd(47): OTHERS choice is never selected" {  } { { "display.vhd" "" { Text "E:/study/eda/TAXT/display.vhd" 47 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "display.vhd(65) " "Info: VHDL Case Statement information at display.vhd(65): OTHERS choice is never selected" {  } { { "display.vhd" "" { Text "E:/study/eda/TAXT/display.vhd" 65 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "display.vhd(83) " "Info: VHDL Case Statement information at display.vhd(83): OTHERS choice is never selected" {  } { { "display.vhd" "" { Text "E:/study/eda/TAXT/display.vhd" 83 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "display.vhd(101) " "Info: VHDL Case Statement information at display.vhd(101): OTHERS choice is never selected" {  } { { "display.vhd" "" { Text "E:/study/eda/TAXT/display.vhd" 101 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "display.vhd(119) " "Info: VHDL Case Statement information at display.vhd(119): OTHERS choice is never selected" {  } { { "display.vhd" "" { Text "E:/study/eda/TAXT/display.vhd" 119 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "display.vhd(137) " "Info: VHDL Case Statement information at display.vhd(137): OTHERS choice is never selected" {  } { { "display.vhd" "" { Text "E:/study/eda/TAXT/display.vhd" 137 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "display.vhd(151) " "Info: VHDL Case Statement information at display.vhd(151): OTHERS choice is never selected" {  } { { "display.vhd" "" { Text "E:/study/eda/TAXT/display.vhd" 151 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "ff_1_s.vhd 2 1 " "Info: Using design file ff_1_s.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ff_1_s-a " "Info: Found design unit 1: ff_1_s-a" {  } { { "ff_1_s.vhd" "" { Text "E:/study/eda/TAXT/ff_1_s.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ff_1_s " "Info: Found entity 1: ff_1_s" {  } { { "ff_1_s.vhd" "" { Text "E:/study/eda/TAXT/ff_1_s.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ff_1_s ff_1_s:inst5 " "Info: Elaborating entity \"ff_1_s\" for hierarchy \"ff_1_s:inst5\"" {  } { { "taxt.bdf" "inst5" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 72 304 424 168 "inst5" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "d_to_b d_to_b:inst1 " "Info: Elaborating entity \"d_to_b\" for hierarchy \"d_to_b:inst1\"" {  } { { "taxt.bdf" "inst1" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 352 488 616 448 "inst1" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "speed speed:inst2 " "Info: Elaborating entity \"speed\" for hierarchy \"speed:inst2\"" {  } { { "taxt.bdf" "inst2" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 272 312 456 400 "inst2" "" } } } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "aq speed.vhd(20) " "Info: (10035) Verilog HDL or VHDL information at speed.vhd(20): object \"aq\" declared but not used" {  } { { "speed.vhd" "" { Text "E:/study/eda/TAXT/speed.vhd" 20 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "frq frq:inst4 " "Info: Elaborating entity \"frq\" for hierarchy \"frq:inst4\"" {  } { { "taxt.bdf" "inst4" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 168 152 272 264 "inst4" "" } } } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "ff_100_s.vhd 2 1 " "Info: Using design file ff_100_s.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ff_100_s-a " "Info: Found design unit 1: ff_100_s-a" {  } { { "ff_100_s.vhd" "" { Text "E:/study/eda/TAXT/ff_100_s.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ff_100_s " "Info: Found entity 1: ff_100_s" {  } { { "ff_100_s.vhd" "" { Text "E:/study/eda/TAXT/ff_100_s.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ff_100_s ff_100_s:inst6 " "Info: Elaborating entity \"ff_100_s\" for hierarchy \"ff_100_s:inst6\"" {  } { { "taxt.bdf" "inst6" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 384 176 296 480 "inst6" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_divide.tdf" 116 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_0nf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_0nf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_0nf " "Info: Found entity 1: lpm_divide_0nf" {  } { { "db/lpm_divide_0nf.tdf" "" { Text "E:/study/eda/TAXT/db/lpm_divide_0nf.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_2jg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_2jg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_2jg " "Info: Found entity 1: sign_div_unsign_2jg" {  } { { "db/sign_div_unsign_2jg.tdf" "" { Text "E:/study/eda/TAXT/db/sign_div_unsign_2jg.tdf" 26 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_9od.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_9od.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_9od " "Info: Found entity 1: alt_u_div_9od" {  } { { "db/alt_u_div_9od.tdf" "" { Text "E:/study/eda/TAXT/db/alt_u_div_9od.tdf" 38 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_ke8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_ke8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_ke8 " "Info: Found entity 1: add_sub_ke8" {  } { { "db/add_sub_ke8.tdf" "" { Text "E:/study/eda/TAXT/db/add_sub_ke8.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_le8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_le8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_le8 " "Info: Found entity 1: add_sub_le8" {  } { { "db/add_sub_le8.tdf" "" { Text "E:/study/eda/TAXT/db/add_sub_le8.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_me8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_me8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_me8 " "Info: Found entity 1: add_sub_me8" {  } { { "db/add_sub_me8.tdf" "" { Text "E:/study/eda/TAXT/db/add_sub_me8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_ne8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_ne8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_ne8 " "Info: Found entity 1: add_sub_ne8" {  } { { "db/add_sub_ne8.tdf" "" { Text "E:/study/eda/TAXT/db/add_sub_ne8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_oe8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_oe8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_oe8 " "Info: Found entity 1: add_sub_oe8" {  } { { "db/add_sub_oe8.tdf" "" { Text "E:/study/eda/TAXT/db/add_sub_oe8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_pe8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_pe8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_pe8 " "Info: Found entity 1: add_sub_pe8" {  } { { "db/add_sub_pe8.tdf" "" { Text "E:/study/eda/TAXT/db/add_sub_pe8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_qe8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_qe8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_qe8 " "Info: Found entity 1: add_sub_qe8" {  } { { "db/add_sub_qe8.tdf" "" { Text "E:/study/eda/TAXT/db/add_sub_qe8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_re8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_re8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_re8 " "Info: Found entity 1: add_sub_re8" {  } { { "db/add_sub_re8.tdf" "" { Text "E:/study/eda/TAXT/db/add_sub_re8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_pa8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_pa8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_pa8 " "Info: Found entity 1: add_sub_pa8" {  } { { "db/add_sub_pa8.tdf" "" { Text "E:/study/eda/TAXT/db/add_sub_pa8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_tmf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_tmf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_tmf " "Info: Found entity 1: lpm_divide_tmf" {  } { { "db/lpm_divide_tmf.tdf" "" { Text "E:/study/eda/TAXT/db/lpm_divide_tmf.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_vig.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_vig.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_vig " "Info: Found entity 1: sign_div_unsign_vig" {  } { { "db/sign_div_unsign_vig.tdf" "" { Text "E:/study/eda/TAXT/db/sign_div_unsign_vig.tdf" 26 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_3od.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_3od.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_3od " "Info: Found entity 1: alt_u_div_3od" {  } { { "db/alt_u_div_3od.tdf" "" { Text "E:/study/eda/TAXT/db/alt_u_div_3od.tdf" 32 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_ma8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_ma8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_ma8 " "Info: Found entity 1: add_sub_ma8" {  } { { "db/add_sub_ma8.tdf" "" { Text "E:/study/eda/TAXT/db/add_sub_ma8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_0ff.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_0ff.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_0ff " "Info: Found entity 1: lpm_divide_0ff" {  } { { "db/lpm_divide_0ff.tdf" "" { Text "E:/study/eda/TAXT/db/lpm_divide_0ff.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "821 " "Info: Implemented 821 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "804 " "Info: Implemented 804 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 11 00:35:27 2008 " "Info: Processing ended: Thu Dec 11 00:35:27 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:33 " "Info: Elapsed time: 00:00:33" {  } {  } 0}  } {  } 0}