taxt.tan.qmsg

FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "8 " "Warning: Found 8 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "ff_100_s:inst6\|cx " "Info: Detected ripple clock \"ff_100_s:inst6\|cx\" as buffer" {  } { { "ff_100_s.vhd" "" { Text "E:/study/eda/TAXT/ff_100_s.vhd" 9 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ff_100_s:inst6\|cx" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "ff_100_s:inst6\|clk_out " "Info: Detected ripple clock \"ff_100_s:inst6\|clk_out\" as buffer" {  } { { "ff_100_s.vhd" "" { Text "E:/study/eda/TAXT/ff_100_s.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ff_100_s:inst6\|clk_out" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "speed:inst2\|kilo " "Info: Detected ripple clock \"speed:inst2\|kilo\" as buffer" {  } { { "speed.vhd" "" { Text "E:/study/eda/TAXT/speed.vhd" 16 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "speed:inst2\|kilo" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "speed:inst2\|mint " "Info: Detected ripple clock \"speed:inst2\|mint\" as buffer" {  } { { "speed.vhd" "" { Text "E:/study/eda/TAXT/speed.vhd" 17 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "speed:inst2\|mint" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "frq:inst4\|clk2 " "Info: Detected ripple clock \"frq:inst4\|clk2\" as buffer" {  } { { "frq.vhd" "" { Text "E:/study/eda/TAXT/frq.vhd" 9 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "frq:inst4\|clk2" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "frq:inst4\|clk_out " "Info: Detected ripple clock \"frq:inst4\|clk_out\" as buffer" {  } { { "frq.vhd" "" { Text "E:/study/eda/TAXT/frq.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "frq:inst4\|clk_out" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "ff_1_s:inst5\|cx " "Info: Detected ripple clock \"ff_1_s:inst5\|cx\" as buffer" {  } { { "ff_1_s.vhd" "" { Text "E:/study/eda/TAXT/ff_1_s.vhd" 9 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ff_1_s:inst5\|cx" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "ff_1_s:inst5\|clk_out " "Info: Detected ripple clock \"ff_1_s:inst5\|clk_out\" as buffer" {  } { { "ff_1_s.vhd" "" { Text "E:/study/eda/TAXT/ff_1_s.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ff_1_s:inst5\|clk_out" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_zj register speed:inst2\|time\[2\] register speed:inst2\|money\[8\] 79.88 MHz 12.519 ns Internal " "Info: Clock \"clk_zj\" has Internal fmax of 79.88 MHz between source register \"speed:inst2\|time\[2\]\" and destination register \"speed:inst2\|money\[8\]\" (period= 12.519 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.292 ns + Longest register register " "Info: + Longest register to register delay is 7.292 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns speed:inst2\|time\[2\] 1 REG LC_X28_Y15_N2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X28_Y15_N2; Fanout = 11; REG Node = 'speed:inst2\|time\[2\]'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "" { speed:inst2|time[2] } "NODE_NAME" } "" } } { "speed.vhd" "" { Text "E:/study/eda/TAXT/speed.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.178 ns) + CELL(0.564 ns) 1.742 ns speed:inst2\|add~1772 2 COMB LC_X29_Y15_N1 2 " "Info: 2: + IC(1.178 ns) + CELL(0.564 ns) = 1.742 ns; Loc. = LC_X29_Y15_N1; Fanout = 2; COMB Node = 'speed:inst2\|add~1772'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "1.742 ns" { speed:inst2|time[2] speed:inst2|add~1772 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.820 ns speed:inst2\|add~1787 3 COMB LC_X29_Y15_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.820 ns; Loc. = LC_X29_Y15_N2; Fanout = 2; COMB Node = 'speed:inst2\|add~1787'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "0.078 ns" { speed:inst2|add~1772 speed:inst2|add~1787 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.898 ns speed:inst2\|add~1862 4 COMB LC_X29_Y15_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.898 ns; Loc. = LC_X29_Y15_N3; Fanout = 2; COMB Node = 'speed:inst2\|add~1862'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "0.078 ns" { speed:inst2|add~1787 speed:inst2|add~1862 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 2.076 ns speed:inst2\|add~1872 5 COMB LC_X29_Y15_N4 4 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 2.076 ns; Loc. = LC_X29_Y15_N4; Fanout = 4; COMB Node = 'speed:inst2\|add~1872'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "0.178 ns" { speed:inst2|add~1862 speed:inst2|add~1872 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 2.697 ns speed:inst2\|add~1795 6 COMB LC_X29_Y15_N6 3 " "Info: 6: + IC(0.000 ns) + CELL(0.621 ns) = 2.697 ns; Loc. = LC_X29_Y15_N6; Fanout = 3; COMB Node = 'speed:inst2\|add~1795'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "0.621 ns" { speed:inst2|add~1872 speed:inst2|add~1795 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.688 ns) + CELL(0.575 ns) 3.960 ns speed:inst2\|add~1742COUT1_1894 7 COMB LC_X30_Y15_N6 2 " "Info: 7: + IC(0.688 ns) + CELL(0.575 ns) = 3.960 ns; Loc. = LC_X30_Y15_N6; Fanout = 2; COMB Node = 'speed:inst2\|add~1742COUT1_1894'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "1.263 ns" { speed:inst2|add~1795 speed:inst2|add~1742COUT1_1894 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 4.568 ns speed:inst2\|add~1645 8 COMB LC_X30_Y15_N7 1 " "Info: 8: + IC(0.000 ns) + CELL(0.608 ns) = 4.568 ns; Loc. = LC_X30_Y15_N7; Fanout = 1; COMB Node = 'speed:inst2\|add~1645'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "0.608 ns" { speed:inst2|add~1742COUT1_1894 speed:inst2|add~1645 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.118 ns) + CELL(0.590 ns) 6.276 ns speed:inst2\|money~1114 9 COMB LC_X27_Y15_N9 1 " "Info: 9: + IC(1.118 ns) + CELL(0.590 ns) = 6.276 ns; Loc. = LC_X27_Y15_N9; Fanout = 1; COMB Node = 'speed:inst2\|money~1114'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "1.708 ns" { speed:inst2|add~1645 speed:inst2|money~1114 } "NODE_NAME" } "" } } { "speed.vhd" "" { Text "E:/study/eda/TAXT/speed.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.707 ns) + CELL(0.309 ns) 7.292 ns speed:inst2\|money\[8\] 10 REG LC_X26_Y15_N9 14 " "Info: 10: + IC(0.707 ns) + CELL(0.309 ns) = 7.292 ns; Loc. = LC_X26_Y15_N9; Fanout = 14; REG Node = 'speed:inst2\|money\[8\]'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "1.016 ns" { speed:inst2|money~1114 speed:inst2|money[8] } "NODE_NAME" } "" } } { "speed.vhd" "" { Text "E:/study/eda/TAXT/speed.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.601 ns 49.38 % " "Info: Total cell delay = 3.601 ns ( 49.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.691 ns 50.62 % " "Info: Total interconnect delay = 3.691 ns ( 50.62 % )" {  } {  } 0}  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "7.292 ns" { speed:inst2|time[2] speed:inst2|add~1772 speed:inst2|add~1787 speed:inst2|add~1862 speed:inst2|add~1872 speed:inst2|add~1795 speed:inst2|add~1742COUT1_1894 speed:inst2|add~1645 speed:inst2|money~1114 speed:inst2|money[8] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.292 ns" { speed:inst2|time[2] speed:inst2|add~1772 speed:inst2|add~1787 speed:inst2|add~1862 speed:inst2|add~1872 speed:inst2|add~1795 speed:inst2|add~1742COUT1_1894 speed:inst2|add~1645 speed:inst2|money~1114 speed:inst2|money[8] } { 0.000ns 1.178ns 0.000ns 0.000ns 0.000ns 0.000ns 0.688ns 0.000ns 1.118ns 0.707ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.621ns 0.575ns 0.608ns 0.590ns 0.309ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.966 ns - Smallest " "Info: - Smallest clock skew is -4.966 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_zj destination 15.707 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_zj\" to destination register is 15.707 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_zj 1 CLK PIN_J4 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 4; CLK Node = 'clk_zj'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "" { clk_zj } "NODE_NAME" } "" } } { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 96 48 216 112 "clk_zj" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.995 ns) + CELL(0.935 ns) 3.399 ns ff_1_s:inst5\|cx 2 REG LC_X9_Y16_N5 1 " "Info: 2: + IC(0.995 ns) + CELL(0.935 ns) = 3.399 ns; Loc. = LC_X9_Y16_N5; Fanout = 1; REG Node = 'ff_1_s:inst5\|cx'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "1.930 ns" { clk_zj ff_1_s:inst5|cx } "NODE_NAME" } "" } } { "ff_1_s.vhd" "" { Text "E:/study/eda/TAXT/ff_1_s.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.556 ns) + CELL(0.935 ns) 4.890 ns ff_1_s:inst5\|clk_out 3 REG LC_X9_Y16_N2 7 " "Info: 3: + IC(0.556 ns) + CELL(0.935 ns) = 4.890 ns; Loc. = LC_X9_Y16_N2; Fanout = 7; REG Node = 'ff_1_s:inst5\|clk_out'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "1.491 ns" { ff_1_s:inst5|cx ff_1_s:inst5|clk_out } "NODE_NAME" } "" } } { "ff_1_s.vhd" "" { Text "E:/study/eda/TAXT/ff_1_s.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.047 ns) + CELL(0.935 ns) 9.872 ns frq:inst4\|clk2 4 REG LC_X8_Y16_N5 1 " "Info: 4: + IC(4.047 ns) + CELL(0.935 ns) = 9.872 ns; Loc. = LC_X8_Y16_N5; Fanout = 1; REG Node = 'frq:inst4\|clk2'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "4.982 ns" { ff_1_s:inst5|clk_out frq:inst4|clk2 } "NODE_NAME" } "" } } { "frq.vhd" "" { Text "E:/study/eda/TAXT/frq.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.556 ns) + CELL(0.935 ns) 11.363 ns frq:inst4\|clk_out 5 REG LC_X8_Y16_N4 28 " "Info: 5: + IC(0.556 ns) + CELL(0.935 ns) = 11.363 ns; Loc. = LC_X8_Y16_N4; Fanout = 28; REG Node = 'frq:inst4\|clk_out'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "1.491 ns" { frq:inst4|clk2 frq:inst4|clk_out } "NODE_NAME" } "" } } { "frq.vhd" "" { Text "E:/study/eda/TAXT/frq.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.633 ns) + CELL(0.711 ns) 15.707 ns speed:inst2\|money\[8\] 6 REG LC_X26_Y15_N9 14 " "Info: 6: + IC(3.633 ns) + CELL(0.711 ns) = 15.707 ns; Loc. = LC_X26_Y15_N9; Fanout = 14; REG Node = 'speed:inst2\|money\[8\]'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "4.344 ns" { frq:inst4|clk_out speed:inst2|money[8] } "NODE_NAME" } "" } } { "speed.vhd" "" { Text "E:/study/eda/TAXT/speed.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.920 ns 37.69 % " "Info: Total cell delay = 5.920 ns ( 37.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.787 ns 62.31 % " "Info: Total interconnect delay = 9.787 ns ( 62.31 % )" {  } {  } 0}  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "15.707 ns" { clk_zj ff_1_s:inst5|cx ff_1_s:inst5|clk_out frq:inst4|clk2 frq:inst4|clk_out speed:inst2|money[8] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "15.707 ns" { clk_zj clk_zj~out0 ff_1_s:inst5|cx ff_1_s:inst5|clk_out frq:inst4|clk2 frq:inst4|clk_out speed:inst2|money[8] } { 0.000ns 0.000ns 0.995ns 0.556ns 4.047ns 0.556ns 3.633ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_zj source 20.673 ns - Longest register " "Info: - Longest clock path from clock \"clk_zj\" to source register is 20.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_zj 1 CLK PIN_J4 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 4; CLK Node = 'clk_zj'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "" { clk_zj } "NODE_NAME" } "" } } { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 96 48 216 112 "clk_zj" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.995 ns) + CELL(0.935 ns) 3.399 ns ff_1_s:inst5\|cx 2 REG LC_X9_Y16_N5 1 " "Info: 2: + IC(0.995 ns) + CELL(0.935 ns) = 3.399 ns; Loc. = LC_X9_Y16_N5; Fanout = 1; REG Node = 'ff_1_s:inst5\|cx'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "1.930 ns" { clk_zj ff_1_s:inst5|cx } "NODE_NAME" } "" } } { "ff_1_s.vhd" "" { Text "E:/study/eda/TAXT/ff_1_s.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.556 ns) + CELL(0.935 ns) 4.890 ns ff_1_s:inst5\|clk_out 3 REG LC_X9_Y16_N2 7 " "Info: 3: + IC(0.556 ns) + CELL(0.935 ns) = 4.890 ns; Loc. = LC_X9_Y16_N2; Fanout = 7; REG Node = 'ff_1_s:inst5\|clk_out'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "1.491 ns" { ff_1_s:inst5|cx ff_1_s:inst5|clk_out } "NODE_NAME" } "" } } { "ff_1_s.vhd" "" { Text "E:/study/eda/TAXT/ff_1_s.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.047 ns) + CELL(0.935 ns) 9.872 ns frq:inst4\|clk2 4 REG LC_X8_Y16_N5 1 " "Info: 4: + IC(4.047 ns) + CELL(0.935 ns) = 9.872 ns; Loc. = LC_X8_Y16_N5; Fanout = 1; REG Node = 'frq:inst4\|clk2'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "4.982 ns" { ff_1_s:inst5|clk_out frq:inst4|clk2 } "NODE_NAME" } "" } } { "frq.vhd" "" { Text "E:/study/eda/TAXT/frq.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.556 ns) + CELL(0.935 ns) 11.363 ns frq:inst4\|clk_out 5 REG LC_X8_Y16_N4 28 " "Info: 5: + IC(0.556 ns) + CELL(0.935 ns) = 11.363 ns; Loc. = LC_X8_Y16_N4; Fanout = 28; REG Node = 'frq:inst4\|clk_out'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "1.491 ns" { frq:inst4|clk2 frq:inst4|clk_out } "NODE_NAME" } "" } } { "frq.vhd" "" { Text "E:/study/eda/TAXT/frq.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.631 ns) + CELL(0.935 ns) 15.929 ns speed:inst2\|mint 6 REG LC_X58_Y16_N8 10 " "Info: 6: + IC(3.631 ns) + CELL(0.935 ns) = 15.929 ns; Loc. = LC_X58_Y16_N8; Fanout = 10; REG Node = 'speed:inst2\|mint'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "4.566 ns" { frq:inst4|clk_out speed:inst2|mint } "NODE_NAME" } "" } } { "speed.vhd" "" { Text "E:/study/eda/TAXT/speed.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.033 ns) + CELL(0.711 ns) 20.673 ns speed:inst2\|time\[2\] 7 REG LC_X28_Y15_N2 11 " "Info: 7: + IC(4.033 ns) + CELL(0.711 ns) = 20.673 ns; Loc. = LC_X28_Y15_N2; Fanout = 11; REG Node = 'speed:inst2\|time\[2\]'" {  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "4.744 ns" { speed:inst2|mint speed:inst2|time[2] } "NODE_NAME" } "" } } { "speed.vhd" "" { Text "E:/study/eda/TAXT/speed.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.855 ns 33.16 % " "Info: Total cell delay = 6.855 ns ( 33.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.818 ns 66.84 % " "Info: Total interconnect delay = 13.818 ns ( 66.84 % )" {  } {  } 0}  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "20.673 ns" { clk_zj ff_1_s:inst5|cx ff_1_s:inst5|clk_out frq:inst4|clk2 frq:inst4|clk_out speed:inst2|mint speed:inst2|time[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "20.673 ns" { clk_zj clk_zj~out0 ff_1_s:inst5|cx ff_1_s:inst5|clk_out frq:inst4|clk2 frq:inst4|clk_out speed:inst2|mint speed:inst2|time[2] } { 0.000ns 0.000ns 0.995ns 0.556ns 4.047ns 0.556ns 3.631ns 4.033ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0}  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "15.707 ns" { clk_zj ff_1_s:inst5|cx ff_1_s:inst5|clk_out frq:inst4|clk2 frq:inst4|clk_out speed:inst2|money[8] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "15.707 ns" { clk_zj clk_zj~out0 ff_1_s:inst5|cx ff_1_s:inst5|clk_out frq:inst4|clk2 frq:inst4|clk_out speed:inst2|money[8] } { 0.000ns 0.000ns 0.995ns 0.556ns 4.047ns 0.556ns 3.633ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } } { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "20.673 ns" { clk_zj ff_1_s:inst5|cx ff_1_s:inst5|clk_out frq:inst4|clk2 frq:inst4|clk_out speed:inst2|mint speed:inst2|time[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "20.673 ns" { clk_zj clk_zj~out0 ff_1_s:inst5|cx ff_1_s:inst5|clk_out frq:inst4|clk2 frq:inst4|clk_out speed:inst2|mint speed:inst2|time[2] } { 0.000ns 0.000ns 0.995ns 0.556ns 4.047ns 0.556ns 3.631ns 4.033ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "speed.vhd" "" { Text "E:/study/eda/TAXT/speed.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "speed.vhd" "" { Text "E:/study/eda/TAXT/speed.vhd" 11 -1 0 } }  } 0}  } { { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "7.292 ns" { speed:inst2|time[2] speed:inst2|add~1772 speed:inst2|add~1787 speed:inst2|add~1862 speed:inst2|add~1872 speed:inst2|add~1795 speed:inst2|add~1742COUT1_1894 speed:inst2|add~1645 speed:inst2|money~1114 speed:inst2|money[8] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.292 ns" { speed:inst2|time[2] speed:inst2|add~1772 speed:inst2|add~1787 speed:inst2|add~1862 speed:inst2|add~1872 speed:inst2|add~1795 speed:inst2|add~1742COUT1_1894 speed:inst2|add~1645 speed:inst2|money~1114 speed:inst2|money[8] } { 0.000ns 1.178ns 0.000ns 0.000ns 0.000ns 0.000ns 0.688ns 0.000ns 1.118ns 0.707ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.621ns 0.575ns 0.608ns 0.590ns 0.309ns } } } { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "15.707 ns" { clk_zj ff_1_s:inst5|cx ff_1_s:inst5|clk_out frq:inst4|clk2 frq:inst4|clk_out speed:inst2|money[8] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "15.707 ns" { clk_zj clk_zj~out0 ff_1_s:inst5|cx ff_1_s:inst5|clk_out frq:inst4|clk2 frq:inst4|clk_out speed:inst2|money[8] } { 0.000ns 0.000ns 0.995ns 0.556ns 4.047ns 0.556ns 3.633ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } } { "E:/study/eda/TAXT/db/taxt_cmp.qrpt" "" { Report "E:/study/eda/TAXT/db/taxt_cmp.qrpt" Compiler "taxt" "UNKNOWN" "V1" "E:/study/eda/TAXT/db/taxt.quartus_db" { Floorplan "E:/study/eda/TAXT/" "" "20.673 ns" { clk_zj ff_1_s:inst5|cx ff_1_s:inst5|clk_out frq:inst4|clk2 frq:inst4|clk_out speed:inst2|mint speed:inst2|time[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "20.673 ns" { clk_zj clk_zj~out0 ff_1_s:inst5|cx ff_1_s:inst5|clk_out frq:inst4|clk2 frq:inst4|clk_out speed:inst2|mint speed:inst2|time[2] } { 0.000ns 0.000ns 0.995ns 0.556ns 4.047ns 0.556ns 3.631ns 4.033ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0}