taxt.tan.qmsg

FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off taxt -c taxt --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off taxt -c taxt --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_zj " "Info: Assuming node \"clk_zj\" is an undefined clock" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 96 48 216 112 "clk_zj" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_zj" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_sp " "Info: Assuming node \"clk_sp\" is an undefined clock" {  } { { "taxt.bdf" "" { Schematic "E:/study/eda/TAXT/taxt.bdf" { { 344 0 168 360 "clk_sp" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_sp" } } } }  } 0}  } {  } 0}