taxt.hier_info

FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。

|taxt
led7s[0] <= display:inst3.led7s[0]
led7s[1] <= display:inst3.led7s[1]
led7s[2] <= display:inst3.led7s[2]
led7s[3] <= display:inst3.led7s[3]
led7s[4] <= display:inst3.led7s[4]
led7s[5] <= display:inst3.led7s[5]
led7s[6] <= display:inst3.led7s[6]
clk_zj => ff_1_s:inst5.clk_in
start => speed:inst2.start
push => speed:inst2.push
clk_sp => ff_100_s:inst6.clk_in
site[0] <= display:inst3.site[0]
site[1] <= display:inst3.site[1]
site[2] <= display:inst3.site[2]
site[3] <= display:inst3.site[3]
site[4] <= display:inst3.site[4]
site[5] <= display:inst3.site[5]


|taxt|display:inst3
clk_d => flg1[1].CLK
clk_d => flg1[0].CLK
clk_d => flg1[2].CLK
q6[0] => led7s6[6].IN19
q6[0] => led7s6[5].IN19
q6[0] => led7s6[4].IN10
q6[0] => led7s6[3].IN19
q6[0] => led7s6[2].IN10
q6[0] => led7s6[1].IN10
q6[0] => led7s6[0].IN19
q6[1] => led7s6[6].IN18
q6[1] => led7s6[5].IN18
q6[1] => led7s6[4].IN9
q6[1] => led7s6[3].IN18
q6[1] => led7s6[2].IN9
q6[1] => led7s6[1].IN9
q6[1] => led7s6[0].IN18
q6[2] => led7s6[6].IN17
q6[2] => led7s6[5].IN17
q6[2] => led7s6[4].IN8
q6[2] => led7s6[3].IN17
q6[2] => led7s6[2].IN8
q6[2] => led7s6[1].IN8
q6[2] => led7s6[0].IN17
q6[3] => led7s6[6].IN16
q6[3] => led7s6[5].IN16
q6[3] => led7s6[3].IN16
q6[3] => led7s6[0].IN16
q5[0] => led7s5[6].IN19
q5[0] => led7s5[5].IN19
q5[0] => led7s5[4].IN10
q5[0] => led7s5[3].IN19
q5[0] => led7s5[2].IN10
q5[0] => led7s5[1].IN10
q5[0] => led7s5[0].IN19
q5[1] => led7s5[6].IN18
q5[1] => led7s5[5].IN18
q5[1] => led7s5[4].IN9
q5[1] => led7s5[3].IN18
q5[1] => led7s5[2].IN9
q5[1] => led7s5[1].IN9
q5[1] => led7s5[0].IN18
q5[2] => led7s5[6].IN17
q5[2] => led7s5[5].IN17
q5[2] => led7s5[4].IN8
q5[2] => led7s5[3].IN17
q5[2] => led7s5[2].IN8
q5[2] => led7s5[1].IN8
q5[2] => led7s5[0].IN17
q5[3] => led7s5[6].IN16
q5[3] => led7s5[5].IN16
q5[3] => led7s5[3].IN16
q5[3] => led7s5[0].IN16
q4[0] => led7s4[6].IN19
q4[0] => led7s4[5].IN19
q4[0] => led7s4[4].IN10
q4[0] => led7s4[3].IN19
q4[0] => led7s4[2].IN10
q4[0] => led7s4[1].IN10
q4[0] => led7s4[0].IN19
q4[1] => led7s4[6].IN18
q4[1] => led7s4[5].IN18
q4[1] => led7s4[4].IN9
q4[1] => led7s4[3].IN18
q4[1] => led7s4[2].IN9
q4[1] => led7s4[1].IN9
q4[1] => led7s4[0].IN18
q4[2] => led7s4[6].IN17
q4[2] => led7s4[5].IN17
q4[2] => led7s4[4].IN8
q4[2] => led7s4[3].IN17
q4[2] => led7s4[2].IN8
q4[2] => led7s4[1].IN8
q4[2] => led7s4[0].IN17
q4[3] => led7s4[6].IN16
q4[3] => led7s4[5].IN16
q4[3] => led7s4[3].IN16
q4[3] => led7s4[0].IN16
q3[0] => led7s3[6].IN19
q3[0] => led7s3[5].IN19
q3[0] => led7s3[4].IN10
q3[0] => led7s3[3].IN19
q3[0] => led7s3[2].IN10
q3[0] => led7s3[1].IN10
q3[0] => led7s3[0].IN19
q3[1] => led7s3[6].IN18
q3[1] => led7s3[5].IN18
q3[1] => led7s3[4].IN9
q3[1] => led7s3[3].IN18
q3[1] => led7s3[2].IN9
q3[1] => led7s3[1].IN9
q3[1] => led7s3[0].IN18
q3[2] => led7s3[6].IN17
q3[2] => led7s3[5].IN17
q3[2] => led7s3[4].IN8
q3[2] => led7s3[3].IN17
q3[2] => led7s3[2].IN8
q3[2] => led7s3[1].IN8
q3[2] => led7s3[0].IN17
q3[3] => led7s3[6].IN16
q3[3] => led7s3[5].IN16
q3[3] => led7s3[3].IN16
q3[3] => led7s3[0].IN16
q2[0] => led7s2[6].IN19
q2[0] => led7s2[5].IN19
q2[0] => led7s2[4].IN10
q2[0] => led7s2[3].IN19
q2[0] => led7s2[2].IN10
q2[0] => led7s2[1].IN10
q2[0] => led7s2[0].IN19
q2[1] => led7s2[6].IN18
q2[1] => led7s2[5].IN18
q2[1] => led7s2[4].IN9
q2[1] => led7s2[3].IN18
q2[1] => led7s2[2].IN9
q2[1] => led7s2[1].IN9
q2[1] => led7s2[0].IN18
q2[2] => led7s2[6].IN17
q2[2] => led7s2[5].IN17
q2[2] => led7s2[4].IN8
q2[2] => led7s2[3].IN17
q2[2] => led7s2[2].IN8
q2[2] => led7s2[1].IN8
q2[2] => led7s2[0].IN17
q2[3] => led7s2[6].IN16
q2[3] => led7s2[5].IN16
q2[3] => led7s2[3].IN16
q2[3] => led7s2[0].IN16
q1[0] => led7s1[6].IN19
q1[0] => led7s1[5].IN19
q1[0] => led7s1[4].IN10
q1[0] => led7s1[3].IN19
q1[0] => led7s1[2].IN10
q1[0] => led7s1[1].IN10
q1[0] => led7s1[0].IN19
q1[1] => led7s1[6].IN18
q1[1] => led7s1[5].IN18
q1[1] => led7s1[4].IN9
q1[1] => led7s1[3].IN18
q1[1] => led7s1[2].IN9
q1[1] => led7s1[1].IN9
q1[1] => led7s1[0].IN18
q1[2] => led7s1[6].IN17
q1[2] => led7s1[5].IN17
q1[2] => led7s1[4].IN8
q1[2] => led7s1[3].IN17
q1[2] => led7s1[2].IN8
q1[2] => led7s1[1].IN8
q1[2] => led7s1[0].IN17
q1[3] => led7s1[6].IN16
q1[3] => led7s1[5].IN16
q1[3] => led7s1[3].IN16
q1[3] => led7s1[0].IN16
site[0] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
site[1] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
site[2] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
site[3] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
site[4] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
site[5] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE
led7s[0] <= Mux~12.DB_MAX_OUTPUT_PORT_TYPE
led7s[1] <= Mux~11.DB_MAX_OUTPUT_PORT_TYPE
led7s[2] <= Mux~10.DB_MAX_OUTPUT_PORT_TYPE
led7s[3] <= Mux~9.DB_MAX_OUTPUT_PORT_TYPE
led7s[4] <= Mux~8.DB_MAX_OUTPUT_PORT_TYPE
led7s[5] <= Mux~7.DB_MAX_OUTPUT_PORT_TYPE
led7s[6] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE


|taxt|ff_1_s:inst5
clk_in => a[2].CLK
clk_in => a[1].CLK
clk_in => a[0].CLK
clk_in => cx.CLK
clk_out <= clk_out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|taxt|d_to_b:inst1
ax[0] => mod~0.IN13
ax[0] => div~0.IN13
ax[0] => div~1.IN16
ax[1] => mod~0.IN12
ax[1] => div~0.IN12
ax[1] => div~1.IN15
ax[2] => mod~0.IN11
ax[2] => div~0.IN11
ax[2] => div~1.IN14
ax[3] => mod~0.IN10
ax[3] => div~0.IN10
ax[3] => div~1.IN13
ax[4] => mod~0.IN9
ax[4] => div~0.IN9
ax[4] => div~1.IN12
ax[5] => mod~0.IN8
ax[5] => div~0.IN8
ax[5] => div~1.IN11
ax[6] => mod~0.IN7
ax[6] => div~0.IN7
ax[6] => div~1.IN10
ax[7] => mod~0.IN6
ax[7] => div~0.IN6
ax[7] => div~1.IN9
ax[8] => mod~0.IN5
ax[8] => div~0.IN5
ax[8] => div~1.IN8
ax[9] => mod~0.IN4
ax[9] => div~0.IN4
ax[9] => div~1.IN7
q3[0] <= div~1.DB_MAX_OUTPUT_PORT_TYPE
q3[1] <= div~1.DB_MAX_OUTPUT_PORT_TYPE
q3[2] <= div~1.DB_MAX_OUTPUT_PORT_TYPE
q3[3] <= div~1.DB_MAX_OUTPUT_PORT_TYPE
q2[0] <= mod~1.DB_MAX_OUTPUT_PORT_TYPE
q2[1] <= mod~1.DB_MAX_OUTPUT_PORT_TYPE
q2[2] <= mod~1.DB_MAX_OUTPUT_PORT_TYPE
q2[3] <= mod~1.DB_MAX_OUTPUT_PORT_TYPE
q1[0] <= mod~0.DB_MAX_OUTPUT_PORT_TYPE
q1[1] <= mod~0.DB_MAX_OUTPUT_PORT_TYPE
q1[2] <= mod~0.DB_MAX_OUTPUT_PORT_TYPE
q1[3] <= mod~0.DB_MAX_OUTPUT_PORT_TYPE


|taxt|speed:inst2
start => q1[8].ACLR
start => q1[7].ACLR
start => q1[6].ACLR
start => q1[5].ACLR
start => q1[4].ACLR
start => q1[3].ACLR
start => q1[2].ACLR
start => q1[1].ACLR
start => q1[0].ACLR
start => q3[8].ACLR
start => q1[9].ACLR
start => q3[7].ACLR
start => q3[6].ACLR
start => q3[5].ACLR
start => q3[4].ACLR
start => q3[3].ACLR
start => q3[2].ACLR
start => q3[1].ACLR
start => q3[0].ACLR
start => q3[9].ACLR
start => q2[4].ACLR
start => q2[3].ACLR
start => q2[2].ACLR
start => q2[1].ACLR
start => q2[0].ACLR
start => q2[5].ACLR
start => time[8].ACLR
start => time[7].ACLR
start => time[6].ACLR
start => time[5].ACLR
start => time[4].ACLR
start => time[3].ACLR
start => time[2].ACLR
start => time[1].ACLR
start => time[0].ACLR
start => time[9].ACLR
push => process4~0.IN0
push => q1[8].ENA
push => q1[7].ENA
push => q1[6].ENA
push => q1[5].ENA
push => q1[4].ENA
push => q1[3].ENA
push => q1[2].ENA
push => q1[1].ENA
push => q1[0].ENA
push => q3[9].ENA
push => q3[8].ENA
push => q3[7].ENA
push => q3[6].ENA
push => q3[5].ENA
push => q3[4].ENA
push => q3[3].ENA
push => q3[2].ENA
push => q3[1].ENA
push => q3[0].ENA
push => q2[5].ENA
push => q2[4].ENA
push => q2[3].ENA
push => q2[2].ENA
push => q2[1].ENA
push => q2[0].ENA
push => q1[9].ENA
clk_1s => q2[4].CLK
clk_1s => q2[3].CLK
clk_1s => q2[2].CLK
clk_1s => q2[1].CLK
clk_1s => q2[0].CLK
clk_1s => mint.CLK
clk_1s => money[9]~reg0.CLK
clk_1s => money[8]~reg0.CLK
clk_1s => money[7]~reg0.CLK
clk_1s => money[6]~reg0.CLK
clk_1s => money[5]~reg0.CLK
clk_1s => money[4]~reg0.CLK
clk_1s => money[3]~reg0.CLK
clk_1s => money[2]~reg0.CLK
clk_1s => money[1]~reg0.CLK
clk_1s => money[0]~reg0.CLK
clk_1s => stance[9]~reg0.CLK
clk_1s => stance[8]~reg0.CLK
clk_1s => stance[7]~reg0.CLK
clk_1s => stance[6]~reg0.CLK
clk_1s => stance[5]~reg0.CLK
clk_1s => stance[4]~reg0.CLK
clk_1s => stance[3]~reg0.CLK
clk_1s => stance[2]~reg0.CLK
clk_1s => stance[1]~reg0.CLK
clk_1s => stance[0]~reg0.CLK
clk_1s => q2[5].CLK
clk_sp => q1[8].CLK
clk_sp => q1[7].CLK
clk_sp => q1[6].CLK
clk_sp => q1[5].CLK
clk_sp => q1[4].CLK
clk_sp => q1[3].CLK
clk_sp => q1[2].CLK
clk_sp => q1[1].CLK
clk_sp => q1[0].CLK
clk_sp => kilo.CLK
clk_sp => q1[9].CLK
stance[0] <= stance[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stance[1] <= stance[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stance[2] <= stance[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stance[3] <= stance[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stance[4] <= stance[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stance[5] <= stance[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stance[6] <= stance[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stance[7] <= stance[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stance[8] <= stance[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stance[9] <= stance[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
money[0] <= money[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
money[1] <= money[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
money[2] <= money[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
money[3] <= money[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
money[4] <= money[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
money[5] <= money[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
money[6] <= money[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
money[7] <= money[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
money[8] <= money[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
money[9] <= money[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|taxt|frq:inst4
clk_in => a[1].CLK
clk_in => a[0].CLK
clk_in => clk2.CLK
clk_out <= clk_out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|taxt|ff_100_s:inst6
clk_in => a[1].CLK
clk_in => a[0].CLK
clk_in => cx.CLK
clk_out <= clk_out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|taxt|d_to_b:inst
ax[0] => mod~0.IN13
ax[0] => div~0.IN13
ax[0] => div~1.IN16
ax[1] => mod~0.IN12
ax[1] => div~0.IN12
ax[1] => div~1.IN15
ax[2] => mod~0.IN11
ax[2] => div~0.IN11
ax[2] => div~1.IN14
ax[3] => mod~0.IN10
ax[3] => div~0.IN10
ax[3] => div~1.IN13
ax[4] => mod~0.IN9
ax[4] => div~0.IN9
ax[4] => div~1.IN12
ax[5] => mod~0.IN8
ax[5] => div~0.IN8
ax[5] => div~1.IN11
ax[6] => mod~0.IN7
ax[6] => div~0.IN7
ax[6] => div~1.IN10
ax[7] => mod~0.IN6
ax[7] => div~0.IN6
ax[7] => div~1.IN9
ax[8] => mod~0.IN5
ax[8] => div~0.IN5
ax[8] => div~1.IN8
ax[9] => mod~0.IN4
ax[9] => div~0.IN4
ax[9] => div~1.IN7
q3[0] <= div~1.DB_MAX_OUTPUT_PORT_TYPE
q3[1] <= div~1.DB_MAX_OUTPUT_PORT_TYPE
q3[2] <= div~1.DB_MAX_OUTPUT_PORT_TYPE
q3[3] <= div~1.DB_MAX_OUTPUT_PORT_TYPE
q2[0] <= mod~1.DB_MAX_OUTPUT_PORT_TYPE
q2[1] <= mod~1.DB_MAX_OUTPUT_PORT_TYPE
q2[2] <= mod~1.DB_MAX_OUTPUT_PORT_TYPE
q2[3] <= mod~1.DB_MAX_OUTPUT_PORT_TYPE
q1[0] <= mod~0.DB_MAX_OUTPUT_PORT_TYPE
q1[1] <= mod~0.DB_MAX_OUTPUT_PORT_TYPE
q1[2] <= mod~0.DB_MAX_OUTPUT_PORT_TYPE
q1[3] <= mod~0.DB_MAX_OUTPUT_PORT_TYPE