taxt.map.rpt

FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。

; CARRY_CHAIN            ; MANUAL         ; Untyped                                 ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                 ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                              ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                            ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                            ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                          ;
+------------------------+----------------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: d_to_b:inst|lpm_divide:mod_rtl_6 ;
+------------------------+----------------+-----------------------------------------+
; Parameter Name         ; Value          ; Type                                    ;
+------------------------+----------------+-----------------------------------------+
; LPM_WIDTHN             ; 10             ; Untyped                                 ;
; LPM_WIDTHD             ; 4              ; Untyped                                 ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                 ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                 ;
; LPM_PIPELINE           ; 0              ; Untyped                                 ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                 ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                 ;
; CBXI_PARAMETER         ; lpm_divide_0ff ; Untyped                                 ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                 ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                 ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                              ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                            ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                            ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                          ;
+------------------------+----------------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: d_to_b:inst|lpm_divide:div_rtl_7 ;
+------------------------+----------------+-----------------------------------------+
; Parameter Name         ; Value          ; Type                                    ;
+------------------------+----------------+-----------------------------------------+
; LPM_WIDTHN             ; 10             ; Untyped                                 ;
; LPM_WIDTHD             ; 7              ; Untyped                                 ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                 ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                 ;
; LPM_PIPELINE           ; 0              ; Untyped                                 ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                 ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                 ;
; CBXI_PARAMETER         ; lpm_divide_0nf ; Untyped                                 ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                 ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                 ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                              ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                            ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                            ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                          ;
+------------------------+----------------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/study/eda/TAXT/taxt.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu Dec 11 00:34:55 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off taxt -c taxt
Info: Found 2 design units, including 1 entities, in source file d_to_b.vhd
    Info: Found design unit 1: d_to_b-one
    Info: Found entity 1: d_to_b
Info: Found 2 design units, including 1 entities, in source file display.vhd
    Info: Found design unit 1: display-a
    Info: Found entity 1: display
Info: Found 2 design units, including 1 entities, in source file frq.vhd
    Info: Found design unit 1: frq-a
    Info: Found entity 1: frq
Info: Found 2 design units, including 1 entities, in source file speed.vhd
    Info: Found design unit 1: speed-a
    Info: Found entity 1: speed
Info: Found 1 design units, including 1 entities, in source file taxt.bdf
    Info: Found entity 1: taxt
Info: Elaborating entity "taxt" for the top level hierarchy
Info: Elaborating entity "display" for hierarchy "display:inst3"
Info: VHDL Case Statement information at display.vhd(47): OTHERS choice is never selected
Info: VHDL Case Statement information at display.vhd(65): OTHERS choice is never selected
Info: VHDL Case Statement information at display.vhd(83): OTHERS choice is never selected
Info: VHDL Case Statement information at display.vhd(101): OTHERS choice is never selected
Info: VHDL Case Statement information at display.vhd(119): OTHERS choice is never selected
Info: VHDL Case Statement information at display.vhd(137): OTHERS choice is never selected
Info: VHDL Case Statement information at display.vhd(151): OTHERS choice is never selected
Info: Using design file ff_1_s.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: ff_1_s-a
    Info: Found entity 1: ff_1_s
Info: Elaborating entity "ff_1_s" for hierarchy "ff_1_s:inst5"
Info: Elaborating entity "d_to_b" for hierarchy "d_to_b:inst1"
Info: Elaborating entity "speed" for hierarchy "speed:inst2"
Info: (10035) Verilog HDL or VHDL information at speed.vhd(20): object "aq" declared but not used
Info: Elaborating entity "frq" for hierarchy "frq:inst4"
Info: Using design file ff_100_s.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: ff_100_s-a
    Info: Found entity 1: ff_100_s
Info: Elaborating entity