taxt.map.summary

来自「FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。」· SUMMARY 代码 · 共 14 行

Flow Status : Successful - Thu Dec 11 00:35:27 2008
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : taxt
Top-level Entity Name : taxt
Family : Cyclone
Device : EP1C20F324C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 804
Total pins : 17
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0