taxt.vhd

FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 5.0 Build 148 04/26/2005 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY taxt IS 
	port
	(
		start :  IN  STD_LOGIC;
		push :  IN  STD_LOGIC;
		clk_sp :  IN  STD_LOGIC;
		clk_zj :  IN  STD_LOGIC;
		led7s :  OUT  STD_LOGIC_VECTOR(6 downto 0);
		site :  OUT  STD_LOGIC_VECTOR(5 downto 0)
	);
END taxt;

ARCHITECTURE bdf_type OF taxt IS 

component d_to_b
	PORT(ax : IN STD_LOGIC_VECTOR(9 downto 0);
		 q1 : OUT STD_LOGIC_VECTOR(3 downto 0);
		 q2 : OUT STD_LOGIC_VECTOR(3 downto 0);
		 q3 : OUT STD_LOGIC_VECTOR(3 downto 0)
	);
end component;

component speed
	PORT(start : IN STD_LOGIC;
		 push : IN STD_LOGIC;
		 clk_1s : IN STD_LOGIC;
		 clk_sp : IN STD_LOGIC;
		 money : OUT STD_LOGIC_VECTOR(9 downto 0);
		 stance : OUT STD_LOGIC_VECTOR(9 downto 0)
	);
end component;

component display
	PORT(clk_d : IN STD_LOGIC;
		 q1 : IN STD_LOGIC_VECTOR(3 downto 0);
		 q2 : IN STD_LOGIC_VECTOR(3 downto 0);
		 q3 : IN STD_LOGIC_VECTOR(3 downto 0);
		 q4 : IN STD_LOGIC_VECTOR(3 downto 0);
		 q5 : IN STD_LOGIC_VECTOR(3 downto 0);
		 q6 : IN STD_LOGIC_VECTOR(3 downto 0);
		 led7s : OUT STD_LOGIC_VECTOR(6 downto 0);
		 site : OUT STD_LOGIC_VECTOR(5 downto 0)
	);
end component;

component frq
	PORT(clk_in : IN STD_LOGIC;
		 clk_out : OUT STD_LOGIC
	);
end component;

component ff_1_s
	PORT(clk_in : IN STD_LOGIC;
		 clk_out : OUT STD_LOGIC
	);
end component;

component ff_100_s
	PORT(clk_in : IN STD_LOGIC;
		 clk_out : OUT STD_LOGIC
	);
end component;

signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC_VECTOR(9 downto 0);
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(9 downto 0);
signal	SYNTHESIZED_WIRE_2 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_3 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_12 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_5 :  STD_LOGIC_VECTOR(3 downto 0);
signal	SYNTHESIZED_WIRE_6 :  STD_LOGIC_VECTOR(3 downto 0);
signal	SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(3 downto 0);
signal	SYNTHESIZED_WIRE_8 :  STD_LOGIC_VECTOR(3 downto 0);
signal	SYNTHESIZED_WIRE_9 :  STD_LOGIC_VECTOR(3 downto 0);
signal	SYNTHESIZED_WIRE_10 :  STD_LOGIC_VECTOR(3 downto 0);


BEGIN 



b2v_inst : d_to_b
PORT MAP(ax => SYNTHESIZED_WIRE_0,
		 q1 => SYNTHESIZED_WIRE_8,
		 q2 => SYNTHESIZED_WIRE_9,
		 q3 => SYNTHESIZED_WIRE_10);

b2v_inst1 : d_to_b
PORT MAP(ax => SYNTHESIZED_WIRE_1,
		 q1 => SYNTHESIZED_WIRE_5,
		 q2 => SYNTHESIZED_WIRE_6,
		 q3 => SYNTHESIZED_WIRE_7);

b2v_inst2 : speed
PORT MAP(start => start,
		 push => push,
		 clk_1s => SYNTHESIZED_WIRE_2,
		 clk_sp => SYNTHESIZED_WIRE_3,
		 money => SYNTHESIZED_WIRE_1,
		 stance => SYNTHESIZED_WIRE_0);

b2v_inst3 : display
PORT MAP(clk_d => SYNTHESIZED_WIRE_12,
		 q1 => SYNTHESIZED_WIRE_5,
		 q2 => SYNTHESIZED_WIRE_6,
		 q3 => SYNTHESIZED_WIRE_7,
		 q4 => SYNTHESIZED_WIRE_8,
		 q5 => SYNTHESIZED_WIRE_9,
		 q6 => SYNTHESIZED_WIRE_10,
		 led7s => led7s,
		 site => site);

b2v_inst4 : frq
PORT MAP(clk_in => SYNTHESIZED_WIRE_12,
		 clk_out => SYNTHESIZED_WIRE_2);

b2v_inst5 : ff_1_s
PORT MAP(clk_in => clk_zj,
		 clk_out => SYNTHESIZED_WIRE_12);

b2v_inst6 : ff_100_s
PORT MAP(clk_in => clk_sp,
		 clk_out => SYNTHESIZED_WIRE_3);

END;