taxt.fit.eqn

FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。

--D1L12 is display:inst3|led7s3[2]~137 at LC_X24_Y22_N8
--operation mode is normal

D1L12 = !Z4L5 & (!Z6L1 & Z5L5);


--D1L41 is display:inst3|led7s2[2]~250 at LC_X25_Y21_N9
--operation mode is normal

D1L41 = M5L91 & (!S62L1 & !M5L02);


--D1L25 is display:inst3|led7s[2]~1759 at LC_X24_Y22_N4
--operation mode is normal

D1L25 = D1_flg1[0] & (D1_flg1[1] # D1L41) # !D1_flg1[0] & !D1_flg1[1] & (D1L7);


--D1L35 is display:inst3|led7s[2]~1760 at LC_X24_Y22_N5
--operation mode is normal

D1L35 = D1_flg1[1] & (D1L25 & D1L82 # !D1L25 & (D1L12)) # !D1_flg1[1] & (D1L25);


--D1L45 is display:inst3|led7s[2]~1761 at LC_X21_Y23_N8
--operation mode is normal

D1L45 = D1_flg1[0] & !Z3L1 & !Z1L5 & Z2L5;


--D1L55 is display:inst3|led7s[2]~1762 at LC_X21_Y23_N6
--operation mode is normal

D1L55 = !D1_flg1[0] & (S91L5 & (!S91_add_sub_cella[1]) # !S91L5 & S5L5);


--D1L65 is display:inst3|led7s[2]~1763 at LC_X21_Y23_N0
--operation mode is normal

D1L65 = D1L45 # D1L55 & !M3L02 & !S6L1;


--D1L75 is display:inst3|led7s[2]~1764 at LC_X24_Y22_N6
--operation mode is normal

D1L75 = D1_flg1[2] & !D1_flg1[1] & D1L65 # !D1_flg1[2] & (D1L35);


--D1L02 is display:inst3|led7s3[1]~138 at LC_X24_Y21_N8
--operation mode is normal

D1L02 = Z4L5 & (Z6L1 $ Z5L5);


--D1L31 is display:inst3|led7s2[1]~251 at LC_X24_Y21_N1
--operation mode is normal

D1L31 = M5L02 & (M5L91 $ S62L1);


--D1L64 is display:inst3|led7s[1]~1765 at LC_X24_Y21_N6
--operation mode is normal

D1L64 = D1_flg1[1] & (D1_flg1[0]) # !D1_flg1[1] & (D1_flg1[0] & D1L31 # !D1_flg1[0] & (D1L6));


--D1L74 is display:inst3|led7s[1]~1766 at LC_X24_Y21_N3
--operation mode is normal

D1L74 = D1L64 & (D1L72 # !D1_flg1[1]) # !D1L64 & D1L02 & D1_flg1[1];


--D1L84 is display:inst3|led7s[1]~1767 at LC_X24_Y21_N4
--operation mode is normal

D1L84 = !D1_flg1[2] & (D1L74);


--D1L94 is display:inst3|led7s[1]~1768 at LC_X21_Y23_N1
--operation mode is normal

D1L94 = D1_flg1[0] & Z1L5 # !D1_flg1[0] & (M3L02);


--D1L43 is display:inst3|led7s5[1]~134 at LC_X21_Y23_N2
--operation mode is normal

D1L43 = S6L1 $ (S91L5 & !S91_add_sub_cella[1] # !S91L5 & (S5L5));


--D1L05 is display:inst3|led7s[1]~1769 at LC_X21_Y23_N3
--operation mode is normal

D1L05 = D1_flg1[0] & (Z3L1 $ Z2L5) # !D1_flg1[0] & D1L43;


--D1L15 is display:inst3|led7s[1]~1770 at LC_X21_Y23_N4
--operation mode is normal

D1L15 = D1L84 # D1L94 & D1L27 & D1L05;


--D1L91 is display:inst3|led7s3[0]~139 at LC_X27_Y22_N6
--operation mode is normal

D1L91 = !Z5L5 & !Y2L5 & (Z6L1 $ Z4L5);


--D1L21 is display:inst3|led7s2[0]~252 at LC_X23_Y23_N1
--operation mode is normal

D1L21 = !M5L91 & !M5L12 & (M5L02 $ S62L1);


--D1L5 is display:inst3|led7s1[0]~255 at LC_X26_Y18_N1
--operation mode is normal

D1L5 = !M6L73 & !M6L93 & (M6L83 $ C1_money[0]);


--D1L24 is display:inst3|led7s[0]~1771 at LC_X23_Y23_N5
--operation mode is normal

D1L24 = D1_flg1[0] & (D1_flg1[1] # D1L21) # !D1_flg1[0] & D1L5 & !D1_flg1[1];


--D1L62 is display:inst3|led7s4[0]~255 at LC_X24_Y23_N7
--operation mode is normal

D1L62 = !M2L73 & !M2L93 & (C1_stance[0] $ M2L83);


--D1L34 is display:inst3|led7s[0]~1772 at LC_X23_Y23_N8
--operation mode is normal

D1L34 = D1_flg1[1] & (D1L24 & D1L62 # !D1L24 & (D1L91)) # !D1_flg1[1] & (D1L24);


--D1L83 is display:inst3|led7s6[0]~111 at LC_X23_Y23_N4
--operation mode is normal

D1L83 = !Z2L5 & !Y1L5 & (Z3L1 $ Z1L5);


--D1L33 is display:inst3|led7s5[0]~135 at LC_X23_Y23_N2
--operation mode is normal

D1L33 = !M3L91 & !M3L12 & (S6L1 $ M3L02);


--D1L44 is display:inst3|led7s[0]~1773 at LC_X23_Y23_N3
--operation mode is normal

D1L44 = D1_flg1[0] & D1L83 # !D1_flg1[0] & (D1L33);


--D1L54 is display:inst3|led7s[0]~1774 at LC_X23_Y23_N9
--operation mode is normal

D1L54 = D1_flg1[2] & !D1_flg1[1] & (D1L44) # !D1_flg1[2] & (D1L34);


--D1L28 is display:inst3|site[5]~76 at LC_X22_Y24_N9
--operation mode is normal

D1L28 = D1_flg1[0] & (D1_flg1[2]);


--D1L18 is display:inst3|site[4]~77 at LC_X22_Y24_N7
--operation mode is normal

D1L18 = !D1_flg1[0] & (D1_flg1[2]);


--D1L08 is display:inst3|site[3]~78 at LC_X21_Y24_N4
--operation mode is normal

D1L08 = D1_flg1[0] & D1_flg1[1];


--D1L97 is display:inst3|site[2]~79 at LC_X21_Y24_N2
--operation mode is normal

D1L97 = !D1_flg1[0] & D1_flg1[1];


--D1L87 is display:inst3|site[1]~80 at LC_X22_Y24_N4
--operation mode is normal

D1L87 = !D1_flg1[1] & D1_flg1[0] & (!D1_flg1[2]);


--D1L77 is display:inst3|site[0]~81 at LC_X22_Y24_N0
--operation mode is normal

D1L77 = !D1_flg1[1] & !D1_flg1[0] & (!D1_flg1[2]);


--F1_clk_out is ff_1_s:inst5|clk_out at LC_X9_Y16_N2
--operation mode is normal

F1_clk_out_lut_out = !F1_clk_out;
F1_clk_out = DFFEAS(F1_clk_out_lut_out, F1_cx, VCC, , , , , , );


--S6L3 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~51 at LC_X21_Y22_N8
--operation mode is arithmetic

S6L3_cout_0 = !M1L73 & !M1L83 & !S6L6;
S6L3 = CARRY(S6L3_cout_0);

--S6L4 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~51COUT1_72 at LC_X21_Y22_N8
--operation mode is arithmetic

S6L4_cout_1 = !M1L73 & !M1L83 & !S6L7;
S6L4 = CARRY(S6L4_cout_1);


--S5L7 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~49 at LC_X18_Y23_N3
--operation mode is arithmetic

S5L7_cout_0 = !M1L03 & !M1L92 & !S5L01;
S5L7 = CARRY(S5L7_cout_0);

--S5L8 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~49COUT1_73 at LC_X18_Y23_N3
--operation mode is arithmetic

S5L8_cout_1 = !M1L03 & !M1L92 & !S5L11;
S5L8 = CARRY(S5L8_cout_1);


--S91L31 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~58 at LC_X17_Y23_N3
--operation mode is arithmetic

S91L31_cout_0 = !M3L81 & !M3L71 & !S91L01;
S91L31 = CARRY(S91L31_cout_0);

--S91L41 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~58COUT1_72 at LC_X17_Y23_N3
--operation mode is arithmetic

S91L41_cout_1 = !M3L81 & !M3L71 & !S91L11;
S91L41 = CARRY(S91L41_cout_1);


--S91L61 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~63 at LC_X17_Y23_N0
--operation mode is arithmetic

S91L61_cout_0 = S91L81;
S91L61 = CARRY(S91L61_cout_0);

--S91L71 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~63COUT1_70 at LC_X17_Y23_N0
--operation mode is arithmetic

S91L71_cout_1 = S91L81;
S91L71 = CARRY(S91L71_cout_1);


--S81L01 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~53 at LC_X17_Y22_N8
--operation mode is arithmetic

S81L01_cout_0 = !M3L21 & !M3L11 & !S81L61;
S81L01 = CARRY(S81L01_cout_0);

--S81L11 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~53COUT1_72 at LC_X17_Y22_N8
--operation mode is arithmetic

S81L11_cout_1 = !M3L21 & !M3L11 & !S81L71;
S81L11 = CARRY(S81L11_cout_1);


--S4L7 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~49 at LC_X18_Y22_N3
--operation mode is arithmetic

S4L7_cout_0 = !M1L42 & !M1L32 & !S4L31;
S4L7 = CARRY(S4L7_cout_0);

--S4L8 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~49COUT1_73 at LC_X18_Y22_N3
--operation mode is arithmetic

S4L8_cout_1 = !M1L42 & !M1L32 & !S4L41;
S4L8 = CARRY(S4L8_cout_1);


--S3L7 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~49 at LC_X18_Y19_N8
--operation mode is arithmetic

S3L7_cout_0 = !M1L81 & !M1L71 & !S3L31;
S3L7 = CARRY(S3L7_cout_0);

--S3L8 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~49COUT1_73 at LC_X18_Y19_N8
--operation mode is arithmetic

S3L8_cout_1 = !M1L81 & !M1L71 & !S3L41;
S3L8 = CARRY(S3L8_cout_1);


--S71L7 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~48 at LC_X17_Y21_N8
--operation mode is arithmetic

S71L7_cout_0 = !M3L5 & !M3L6 & !S71L31;
S71L7 = CARRY(S71L7_cout_0);

--S71L8 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~48COUT1_72 at LC_X17_Y21_N8
--operation mode is arithmetic

S71L8_cout_1 = !M3L5 & !M3L6 & !S71L41;
S71L8 = CARRY(S71L8_cout_1);


--M3L7 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[36]~23 at LC_X17_Y22_N2
--operation mode is normal

M3L7 = !S71L5 & S3L5;


--M3L8 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[36]~28 at LC_X17_Y22_N1
--operation mode is normal

M3L8 = S71L5 & !S71_add_sub_cella[1];


--S81L31 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~58 at LC_X17_Y22_N5
--operation mode is arithmetic

S81L31_cout_0 = S81L81;
S81L31 = CARRY(S81L31_cout_0);

--S81L41 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~58COUT1_70 at LC_X17_Y22_N5
--operation mode is arithmetic

S81L41_cout_1 = S81L81;
S81L41 = CARRY(S81L41_cout_1);


--Z3L3 is d_to_b:inst|lpm_divide:div_rtl_7|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_re8:add_sub_9|add_sub_cella[3]~71 at LC_X23_Y21_N6
--operation mode is arithmetic

Z3L3_cout_0 = !W1L13 & !W1L23 & !Z3L6;
Z3L3 = CARRY(Z3L3_cout_0);

--Z3L4 is d_to_b:inst|lpm_divide:div_rtl_7|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_re8:add_sub_9|add_sub_cella[3]~71COUT1_103 at LC_X23_Y21_N6
--operation mode is arithmetic